DIC10

1. contains two independent or identical 2 to 4 decoders

(a) 74X119

(b) 74X139

(c) 74X129

(d) 74X130

 

2. If ABCD represents naturally BCD, PQRST represents 2 out of 5 code, then Q is

(a) BC + BD + A1C1D1

(b) BC1 + BD1 + ACD

(c) BC1 + BD + A1CD1

(d) BC1 + BD1 + A1C1D1

 

3. is a priority encoder

(a) 74 × 144

(b) 74 × 148

(c) 74 × 48

(d) 74 × 146

 

4. EO L signal is an enable output designed to be connected to input of another 74 ×148.

(a) EO H

(b) EI H

(c) EO L

(d) EI L

 

5. 74 × 541 input has of hysteris

(a) 0.8V

(b) 0.6V

(c) 0.4 V

(d) 0.3V

 

6. is 2 input, 4 bit multiplexer.

(a) 74 × 541

(b) 74 × 148

(c) 74 × 157

(d) 74 × 155

 

7. Three state outputs in multiplexer useful when

(a) n input multiplexers are combined to form larger multiplexer.

(b) n input multiplexers are combined to form larger demultiplexer

(c) n -1 input multiplexers are combined to form larger demultiplexer

(d) n -1 input multiplexers are combined to form larger multiplexer

 

8. A block of flats has four floors and it is arranged that the lights for the stair well can be switched on or off at any

floor level.When the switch on, that level is operated. If switches on the four levels A, B ,C, & D and lights L ,the

Boolean expression for L is

(a) A B _ C _ D

(b) A _ B _ C _ D

(c) A _ B C _ D

(d) A _ B _ C D

 

9. Parity checking function Fe for even parity is

(a) D2 _ D1 _ D0

(b) D2 _ D1 _ P0

(c) [D2 _ D1 _ D0 _ P0]1

(d) D2 _ D1 _ D0 _ P0

 

10. In 74 × 283, carry Ci+1 is

(a) (xi + yi).(xiyi + Ci)

(b) (xi + yi).(xiyi + Ci)1

(c) (xi + yi). _ (xiyi + Ci)

(d) (xi + yi)1. + (xiyi + Ci)

 

11. For 74 x 182, Ci+1 is

(a) (xiyi+xi+yi) _ (xi+yi+Ci)

(b) (xi+yi+xi+yi)(xi+yi+Ci)

(c) (xiyi+xi+yi)(xiyi+Ci)

(d) (xi+yi+xi+yi)(xiyi _ Ci)

 

12. 24 bit comparator uses

(a) two 74 x 682, two 74 x 29, two 74 x 03

(b) three 74 x 682, two 74 x 27, three 74 x 02

(c) four 74 x 684, three74 x 27, three 74 x 02

(d) three 74 x 682, one 74 x 27, two 74 x 02

 

13. 74LS109 has the following characteristic equation.

(a) Q_ = S + R1.Q

(b) Q_ = D

(c) Q_ = J.Q1 + K L.Q

(d) Q_ = EN.D + EN1.Q

 

14. For proper circuit operation

(a) tclk − tffpd > tcombtsetup

(b) tclk − tffpd − tcomb = tsetup

(c) tclk − tffpd − tcomb > tsetup

(d) tclk − tffpd − tcomb <>setup

 

15. is 6 bit register.

(a) 74 × 112

(b) 74 × 174

(c) 74 × 375

(d) 74 × 75

 

16. GAL22V10 has tCF =

(a) 12 or 3.5

(b) 5 or 20

(c) 13 or 2.5

(d) 10 or 1.5

 

17. is 8 bit serial in parallel out shift register.

(a) 74 × 112

(b) 74 × 74

(c) 74 × 164

(d) GAL22V10

 

18. structure eliminate clock skew in ASIC.

(a) clock tree

(b) equalizers

(c) synchronizers

(d) clock latency

 

19. For 74HC04, low level is

(a) = 1.35 V

(b) > 1.35V

(c) < 1.5V

(d) < 1.35V

 

20. is 8K × 8 SRAM.

(a) GAL22V10

(b) 2764

(c) 74HC04

(d) HM6264

DIC9

1. One of the following is 3 to 8 decoder

(a) 74X138

(b) 74X130

(c) 74X36

(d) 74X119

 

2. If I0 to I7 are inputs and Y0 to Y2 are outputs of 8 to 3 encoder, then Y2 in terms of inputs is

(a) I4 + I5 + I6 + I1

(b) I4 + I3 + I6 + I7

(c) I4 + I5 + I6 + I7

(d) I4 + I5 + I2 + I7

 

3. 0XX011111 gives output in priority encoder

(a) 10001

(b) 10101

(c) 00101

(d) 10100

 

4. Shown in figure 4 represents

Figure 4

(a) Inverting active high enable buffer

(b) non Inverting active high enable buffer

(c) Non - inverting active low enable buffer

(d) inverting active low enable buffer

 

5. 74 × 541 input has of hysteris

(a) 0.8V

(b) 0.3V

(c) 0.6V

(d) 0.4 V

 

6. General logic equation for multiplexer output: Iy is

(a)

N−1 Pj=0

EN.Mj.iDj

(b)

N−1 Pj=0

EN.iDj

(c)

N−1 Pj=0

EN.Mi

(d)

N−1 Pj=0

Mi.iDj

7. The square of three bit binary number A2A1A0 is represented as PQRSTU. Then Boolean expression for Q is

(a) (A11

A10

_ A1A0)

(b) A2(A1A0)

(c) A2(A11

A0 + A1 + A0)

(d) A2(A11

A10

+ A1A0)

 

8. The square of three bit binary number A2A1A0 is represented as PQRSTU. Then

Boolean expression for P is

(a) A2A0 _ A2A1

(b) A2A0 + A2A1

(c) A2A0 + A2 _ A1

(d) A2A0 + A2A1A0

 

9. The square of three bit binary number A2A1A0 is represented as PQRSTU. Then Boolean expression for S is

(a) A2A0 + A2A1

(b) (A11

A10

_ A1A0)

(c) (A11

A10

_ A1)

(d) A1A0

 

10. is 4 bit ALU.

(a) 74 × 280

(b) 74 × 153

(c) 74 × 138

(d) 74 × 181

 

11. For 74 x 182, Ci+1 is

(a) (xiyi+xi+yi)(xiyi+Ci)

(b) (xiyi+xi+yi) _ (xi+yi+Ci)

(c) (xi+yi+xi+yi)(xiyi _ Ci)

(d) (xi+yi+xi+yi)(xi+yi+Ci)

 

12. One of the following VHDL statement is used for Fixed point to floating point conversion

(a) if BV < 14 ,then M < = B (2down to 0); E < = “010“;

(b) if BV < 16 ,then M < = B (3down to 0); E < = “000“;

(c) if BV < 15 ,then M < = B (3down to 1); E < = “001“;

(d) if BV < 10 ,then M < = B (3down to 2); E < = “100“;

 

13. is a TTL positive edge trigger JKFF with active low K input.

(a) 74 × 190

(b) 74 × 109

(c) 74 × 10

(d) 74LS74

 

14. S - R latch characteristic equation is

(a) S + R1.Q1

(b) Q_ = S + R1.Q

(c) S1 + R1.Q

(d) S1 + R1.Q1

 

15. is ( octal edge trigger D FF) 8 bit register.

(a) 74 × 74

(b) 74 × 112

(c) 74 × 374

(d) 74 × 174

 

16. Little rectangular symbols inside the buffer symbols indicate

(a) amplification

(b) inverter

(c) inductance

(d) Hysterisis

 

17. In ring counter using 74 × 194, LIN serial input connected to

(a) CLR L

(b) TE

(c) QA

(d) QA1

 

18. A method of gating the clock that generates only minimal clock skew is

(a) gates in different IC package is used to generate ungated clock and gated clocks from same master clock signal.

(b) using of equalizers and digital delay lines

(c) gates in same IC package is used to generate ungated clock and gated clocks from different master clock signal.

(d) gates in same IC package is used to generate un gated clock and gated clocks from same master clock signal.

 

19. For 74HC04, low level is

(a) < 1.5V

(b) < 1.35V

(c) > 1.35V

(d) = 1.35 V

 

20. contains separate OE L control input.

(a) Extended data out DRAM

(b) SSRAM

(c) SDRAM

(d) LATE WRITE SSRAMb