DIC4

1. One of the following is 3 to 8 decoder

(a) 74X130

(b) 74X119

(c) 74X36

(d) 74X138

 

2. 10011 input in seven segment decodes as output.

(a) 1111101

(b) 1011001

(c) 1111001

(d) 1111000

 

3. is a priority encoder

(a) 74 × 146

(b) 74 × 148

(c) 74 × 144

(d) 74 × 48

 

4. The purpose of conv std logic vector (j, n) in VHDL coding of 74 × 148, 8 input priority encoder is to convert

integer j to

(a) std logic vector

(b) std ulogic

(c) real

(d) std logic

 

5. contains inverting buffer

(a) 74543

(b) 74540

(c) 74504

(d) 74542

 

6. For 74 × 151, input 0001 produces

(a) D5&D61

(b) D1&D11

(c) D5&D51

(d) D1&D21

 

7. is 9 bit parity generator.

(a) 74 × 138

(b) 74 × 280

(c) 74 × 86

(d) 74 × 153

 

8. is 4 bit comparator.

(a) 74 × 280

(b) 74 × 153

(c) 74 × 85

(d) 74 × 138

 

9. is quadruple 2 input XOR gate.

(a) 74 × 153

(b) 74 × 280

(c) 74 × 86

(d) 74 × 138

 

10. Borrow out in full sub tractor VHDL code is

(a) bout < = ( not X and bin) nor ( not X nand y) or ( bin and Y);

(b) bout < = ( not X n and bin) or ( not X and y) nor ( bin and Y);

(c) bout < = ( not X and bin) nor ( not X and y) or ( bin nand Y);

(d) bout < = ( not X and bin) or ( not X and Y) or ( bin and Y);

 

11. For 74 x 382, if S2 S1 S0 =110, then F is

(a) A1B1

(b) A · B

(c) A _ B

(d) A1 _ B

 

12. A combinational fixed point to floating point encoder consists of

(a) 74 x 280,two 74 x 138

(b) one 74 x 148, three 74 x 154

(c) one 74 x 148, two 74 x 154, 74 x 251

(d) two 74 x 154, 74 x 251

 

13. 74LS74 characteristic equation is

(a) Q_ = D

(b) Q_ = S + R1.Q

(c) Q_ = EN.D + EN1.Q

(d) Q_ = J.Q0 + K L.Q

 

14. If is negative, the circuit don’t work.

(a) set up time margin

(b) tcomb(min)

(c) Hold time margin

(d) tffpd(min)

 

15. consider Bus holder circuit in 3.3V CMOS LVC. Specify a maximum over ride cutoff

(a) 200 micro A

(b) 500 μ A

(c) 300micro A

(d) 100 mA

 

16. GAL22V10 has tCF =

(a) 5 or 20

(b) 12 or 3.5

(c) 13 or 2.5

(d) 10 or 1.5

 

17. In 74 × 299, bits shifted right if

(a) S1 =1 , SD =1

(b) S1 =1, SD =0

(c) S1 =0 , SD =1

(d) S1 =0 , SD =0

 

18. MTBF (tr) is

(a) [log(tr/_)]/[T1.f.a]

(b) [exp(tr/_)]/[T0.f.a]

(c) [erfc(tr/_)]/[T0.f.a2]

(d) [exp(tr)][T0.f ]

 

19. EPROM (CMOS Technology) Write cycle is

(a) 50 - 100 μs /byte

(b) 70 - 500 μs /byte

(c) 10 - 50 μs/byte

(d) 100 - 500 μs /byte

 

20. In SRAMs output buffer is automatically disabled whenever is asserted ,even if OE L is asserted.

(a) CLR H

(b) WE L

(c) CLR L

(d) WE H