DIC5

1. One of the following is 3 to 8 decoder

(a) 74X119

(b) 74X138

(c) 74X130

(d) 74X36

 

2. If G1,G2A,G2B are enable inputs, C,B,A are inputs, then output Y5 in terms of enable & input signal for 3 to 8

decoder is

(a) G2A.G2B.C.B1.A

(b) G1.G2A.G2B.B1.A

(c) G1.G2A.G2B.C.B1.A

(d) G1.G2A.G2B.C.B1

 

3. The IDLE output in generic 8 input priority encoder is asserted if are asserted.

(a) no inputs

(b) I2,I6

(c) I4,I5

(d) I1, I4

 

4. used to describe prioritization in VHDL.

(a) while

(b) assert

(c) if then else

(d) port

 

5. in 74 × 245 determines direction of transfer

(a) G1 L

(b) G L

(c) G2 L

(d) dir

 

6. For 74 × 151, input 0001 produces

(a) D5&D61

(b) D1&D11

(c) D5&D51

(d) D1&D21

 

7. is 9 bit parity generator.

(a) 74 × 86

(b) 74 × 280

(c) 74 × 138

(d) 74 × 153

 

8. is 4 bit comparator.

(a) 74 × 280

(b) 74 × 85

(c) 74 × 138

(d) 74 × 153

 

9. If the input & output signal voltage levels(L& H) are indicated in truth table,

then it is also known as

(a) excitation table

(b) state diagram

(c) state table

(d) function table

 

10. Total propagation delay from C0 to C16 in 16 bit group ripple adder using 74 × 283 is

(a) same as that of six inverting gates

(b) same as that of four inverting gates

(c) same as that of eight inverting gates.

(d) twice the eight inverting gates

 

11. In 24 bit comparator circuit PGTQ is

(a) GT2 + EQ21. _ GT1 + EQ21. _ EQ1.GT0

(b) GT2+EQ2 . GT1 + EQ2. EQ1 . GT0

(c) GT21 _ EQ2.GT1 _ EQ2.EQ1.GT0

(d) GT2 + EQ21.GT1 _ EQ2.EQ1.GT01

 

12. 74x682 does not provide

(a) output

(b) less than output

(c) greater than output

(d) equal output

 

13. In JK master slave FF, because of the gating on master latches S& R inputs, FF output change to1 even though K

and not J is asserted at the end of the Triggering pulse.This behaviour known as

(a) Z latching

(b) 0s latching

(c) don’t care latching

(d) 1’s latching

 

14. The sum of minimum values of tffpd and tcomb must be

(a) greater than tsetup

(b) less than Set up time margin

(c) less than tclk

(d) greater than thold

 

15. consider Bus holder circuit in 3.3V CMOS LVC. Specify a maximum over ride cutoff

(a) 500 μ A

(b) 200 micro A

(c) 100 mA

(d) 300micro A

 

16. GAL22V10 has tCF =

(a) 5 or 20

(b) 13 or 2.5

(c) 10 or 1.5

(d) 12(b) 74X138

 

17. LFSR also known as

(a) minimum length sequence generator

(b) maximum length sequence generator

(c) Johnson counter

(d) shift circular register

 

18. Metastability resolution time, tr is

(a) tclk + tcomb + tsetup

(b) tclk − tcomb − tsetup

(c) tclk − tcomb + tsetup

(d) tclk − tcombtsetup

 

19. EPROM (CMOS Technology) Write cycle is

(a) 50 - 100 μs /byte

(b) 10 - 50 μs/byte

(c) 70 - 500 μs /byte

(d) 100 - 500 μs /byte

 

20. In SRAMs output buffer is automatically disabled whenever is asserted ,even if OE L is asserted.

(a) WE H

(b) WE L

(c) CLR H

(d) CLR L