DIC6

1. 74 × 138 has

(a) one enable input

(b) two enable inputs

(c) three enable inputs

(d) four enable inputs

 

2. 10111 input gives output in seven segment decoder

(a) 1110001

(b) 1100000

(c) 1110010

(d) 1110000

 

3. 74 × 148 inputs are

(a) buffered & inverted

(b) active high

(c) active low

(d) inverted

 

4. EO L signal is an enable output designed to be connected to input of another 74 ×148.

(a) EO H

(b) EI H

(c) EO L

(d) EI L

 

5. in 74 × 245 determines direction of transfer

(a) G L

(b) G1 L

(c) dir

(d) G2 L

 

6. For 74 × 151, input 0101 produces

(a) D5&D51

(b) D5&D61

(c) D1&D11

(d) D1&D21

 

7. has three state outputs.

(a) 74 × 541

(b) 74 × 153

(c) 74 × 148

(d) 74 × 251

 

8. AEQB out in 74 × 85 is equal to

(a) (A > B) + (A = B).AGTBIN

(b) (A = B).AEQBIN

(c) (A <>) + (A = B).ALTBIN

(d) (A > B) + (A = B)

 

9. If D2,D1 and D0 are three bit input to parity generator, then Pe is even parity bit. Boolean expression for Pe in

terms of D2,D1,D0 is

(a) D2 _ D1 + D0

(b) D2D1 _ D0

(c) D2 _ D1 _ D0

(d) D2 _ D1D0

 

10. In 74 × 283, carry Ci+1 is

(a) (xi + yi).(xiyi + Ci)1

(b) (xi + yi). _ (xiyi + Ci)

(c) (xi + yi).(xiyi + Ci)

(d) (xi + yi)1. + (xiyi + Ci)

 

11. In 24 bit comparator circuit PGTQ is

(a) GT2 + EQ21.GT1 _ EQ2.EQ1.GT01

(b) GT2+EQ2 . GT1 + EQ2. EQ1 . GT0

(c) GT2 + EQ21. _ GT1 + EQ21. _ EQ1.GT0

(d) GT21 _ EQ2.GT1 _ EQ2.EQ1.GT0

 

12. In 24 bit comparator circuit, PEQQ is

(a) EQ2 _ .EQ1.EQ01

(b) EQ2 _ .EQ1. _ EQ0

(c) EQ2.EQ1.EQ0

(d) EQ2. + EQ1. _ EQ0

 

13. 74LS74 characteristic equation is

(a) Q_ = D

(b) Q_ = S + R1.Q

(c) Q_ = EN.D + EN1.Q

(d) Q_ = J.Q0 + K L.Q

 

14. For proper circuit operation

(a) tclk − tffpd − tcomb > tsetup

(b) tclk − tffpd > tcombtsetup

(c) tclk − tffpd − tcomb = tsetup

(d) tclk − tffpd − tcomb <>setup

 

15. In 74 ×175, are buffered.

(a) clock and CLR L

(b) CLR, Q

(c) 1Q

(d) clock, D

16. GAL22V10 has tCF =

(a) 12 or 3.5

(b) 13 or 2.5

(c) 5 or 20

(d) 10 or 1.5

 

17. LFSR also known as

(a) shift circular register

(b) maximum length sequence generator

(c) minimum length sequence generator

(d) Johnson counter

 

18. A method of gating the clock that generates only minimal clock skew is

(a) gates in different IC package is used to generate ungated clock and gated clocks from same master clock signal.

(b) using of equalizers and digital delay lines

(c) gates in same IC package is used to generate ungated clock and gated clocks from different master clock signal.

(d) gates in same IC package is used to generate un gated clock and gated clocks from same master clock signal.

 

19. EPROM (CMOS Technology) Write cycle is

(a) 100 - 500 μs /byte

(b) 10 - 50 μs/byte

(c) 50 - 100 μs /byte

(d) 70 - 500 μs /byte

 

20. supports burst mode.

(a) ZBT SSRAM with pipelined outputs

(b) SRAMs output buffer

(c) late write SSRAM with flow through outputs

(d) Extended data out DRAM