DIC7

1. One of the following is 3 to 8 decoder

(a) 74X36

(b) 74X138

(c) 74X119

(d) 74X130

 

2. The 1 out of 2n coded outputs of n bit binary decoder used to control a set of

(a) 2 n devices

(b) 2n devices

(c) 2n−1 devices

(d) 2n+1 devices

 

3. The Boolean expression for output A0 of generic 8 input priority encoder in terms of intermediate variable H0 to

H7 is

(a) H1 + H3 + H5 + H7

(b) H0 + H3 + H5 + H7

(c) H1 + H3 + H5 + H6

(d) H1 + H2 + H5 + H7

 

4. EO L signal is an enable output designed to be connected to input of another 74 ×148.

(a) EI L

(b) EI H

(c) EO H

(d) EO L

 

5. 74 × 541 input has of hysteris

(a) 0.6V

(b) 0.3V

(c) 0.8V

(d) 0.4 V

 

6. In 74 × 245, if G=0 and dir = 1 indicate

(a) trans receive independently depending Al also

(b) transfer data from a source on bus A to a destination bus B

(c) transfer data from a source on bus B to a destination bus A

(d) transfer data independently

 

7. Three state outputs in multiplexer useful when

(a) n -1 input multiplexers are combined to form larger demultiplexer

(b) n input multiplexers are combined to form larger demultiplexer

(c) n input multiplexers are combined to form larger multiplexer.

(d) n -1 input multiplexers are combined to form larger multiplexer

 

8. AEQB out in 74 × 85 is equal to

(a) (A > B) + (A = B).AGTBIN

(b) (A <>) + (A = B).ALTBIN

(c) (A = B).AEQBIN

(d) (A > B) + (A = B)

 

9. The square of three bit binary number A2A1A0 is represented as PQRSTU. Then Boolean expression for S is

(a) (A11

A10

_ A1A0)

(b) (A11

A10

_ A1)

(c) A2A0 + A2A1

(d) A1A0

 

10. Total worst case delay in ripple adder tadd is

(a) tXY Cout + (n − 3).CCin + tCinS

(b) tXY (n − 2).CCinCout + tCinS

(c) tXY Cout + (n − 2).CCinCout + tCinS

(d) tXY Cout + (n − 1).CCinCouttCinS

 

11. For 74 x 182, Ci+1 is

(a) (xi+yi+xi+yi)(xiyi _ Ci)

(b) (xiyi+xi+yi) _ (xi+yi+Ci)

(c) (xi+yi+xi+yi)(xi+yi+Ci)

(d) (xiyi+xi+yi)(xiyi+Ci)

 

12. First and second highest priority encoder circuit uses

(a) three 74LS148, one 74LS138, four74LS04, two74LS00

(b) one 74LS148, one 74LS138,two74LS04, three74LS00

(c) four 74LS148, four 74LS138, two74LS04,74LS00

(d) two 74LS148, one 74LS138, 74LS04, 74LS00

 

13. Important Flip Flop function for ASIC testing is

(a) input capability

(b) output capability

(c) switching capability

(d) scan capability

 

14. For proper circuit operation

(a) tclk − tffpd > tcombtsetup

(b) tclk − tffpd − tcomb > tsetup

(c) tclk − tffpd − tcomb = tsetup

(d) tclk − tffpd − tcomb <>setup

15. is JKFF with active low clock input.

(a) 74 × 112

(b) 74 × 175

(c) 74 × 375

(d) 74 × 74

 

16. is first generation sequential PLD.

(a) PAL16R8

(b) GAL16V8R

(c) PAL20L8

(d) PAL20L10

 

17. In ring counter using 74 × 194, LIN serial input connected to

(a) QA1

(b) CLR L

(c) TE

(d) QA

 

18. For reliable synchronous design , one of the following is valid.

(a) maximize amount of clock skew

(b) minimize amount of clock skew

(c) ensure FF have negative set up & hold time marging

(d) synchronizers should have medium probability of failure

 

19. EEPROM ( NMOS Technology) Read cycle is

(a) 250 -1 200ms

(b) 250 - 300ns

(c) 500 - 1500ns

(d) 50 - 200 ns

 

20. RAS to CAS delay is known as

(a) RAS recovery time

(b) CAS latency

(c) RAS latency

(d) CAS propagation time