DIC

1. If ABCD represents naturally BCD, PQRST represents 2 out of 5 code, then S is

(a) AD1 + A1C1D + A1B1D

(b) AD1 + ACD1 + ABD

(c) AD1 + ACD + AB

(d) AD1 + ACD + ABD1

2. If I0 to I7 are inputs and Y0 to Y2 are outputs of 8 to 3 encoder, then Y2 in terms of inputs is

(a) I4 + I5 + I6 + I7

(b) I4 + I5 + I2 + I7

(c) I4 + I5 + I6 + I1

(d) I4 + I3 + I6 + I7

3. If ABCD represents naturally BCD, PQRST represents 2 out of 5 code, then T is

(a) BC1D1 + BCD + B1CD + A1B1CD

(b) BC1D + BCD + BCD1 + A1B1C1D

(c) BC1D1 + BCD + B1CD1 + A1B1C1D

(d) BC1D1 + BCD + BCD1 + ABC1D

4. must be asserted for any of its output to be asserted in 74 × 148

(a) EO L

(b) EI L

(c) EI H

(d) EO H

5. In 74 × 245, if G=0 and dir = 0 indicate

(a) transfer data independently

(b) trans receive depending on chip enable

(c) transfer data from a source on bus A to a destination bus B

(d) transfer data from a source on bus B to a destination bus A

6. General logic equation for multiplexer output: Iy is

(a)

N−1 Pj=0

EN.Mj.iDj

(b)

N−1 Pj=0

EN.iDj

(c)

N−1 Pj=0

EN.Mi

(d)

N−1 Pj=0

Mi.iDj

7. is 4 input , 2 bit multiplexer

(a) 74 × 541

(b) 74 × 148

(c) 74 × 153

(d) 74 × 151

8. The square of three bit binary number A2A1A0 is represented as PQRSTU. Then Boolean expression for U is

(a) A2A0 _ A2A1

(b) A2A0 + A2A1A0

(c) (A11

A10

_ A1A0)

(d) A0

9. if then else VHDL statement used within

(a) assert

(b) select

(c) process

(d) WHILE

10. The VHDL code for difference bit in full sub tractor is

(a) diff <= x XOR Y XOR bin ;

(b) diff <= xNANDY ORbin;

(c) diff <= xXNORY XORbin;

(d) diff <= xXNORY ORbin;

11. specify the direction of shift, type of shift and amount of shift.

(a) Carry save shifter

(b) Barrel shifter

(c) sequential shifter

(d) group ripple shifter

12. 74x682 does not provide

(a) equal output

(b) greater than output

(c) less than output

(d) output

13. Flip Flops with postponed output indicator (Master - slave S R FF) are called

(a) negative edge triggered T Flip Flop with scan.

(b) negative edge triggered JK Flip Flop with scan.

(c) positive edge triggered D Flip Flop with scan

(d) pulse triggered Flip Flop

 

14. D FF with enable characteristic equation is

(a) Q_ = EN1.D + EN1.Q1

(b) Q_ = EN.D + EN.Q

(c) Q_ = EN.D + EN1.Q

(d) Q_ = EN1.D + EN1.Q

15. is ( octal edge trigger D FF) 8 bit register.

(a) 74 × 374

(b) 74 × 74

(c) 74 × 174

(d) 74 × 112

16. is first generation sequential PLD.

(a) GAL16V8R

(b) PAL20L10

(c) PAL16R8

(d) PAL20L8

17. In serial to parallel conversion using parallel out shift register, the following ICs are used.

(a) threee 74 × 163, one 74 × 164, two 74 × 04, two74 × 27, one 74 × 377.

(b) two 74 × 163, one 74 × 164, three 74 × 04, one 74 × 27, two74 × 377.

(c) two 74 ×163, one 74 × 164, two 74 × 04, one 74 × 27, one 74 × 377

(d) two 74 × 163, four74 × 164, three 74 × 04, one 74 × 27, one 74 × 377.

 

18. For reliable synchronous design , one of the following is valid.

(a) maximize amount of clock skew

(b) ensure FF have negative set up & hold time marging

(c) minimize amount of clock skew

(d) synchronizers should have medium probability of failure

 

19. A 1M × 1 ROM could be built with

(a) 10 to 1024 decoder and 1024 input multiplexer

(b) floating source MOS

(c) 3 to 10 decoder and 20 input multiplexer

(d) 3 to 8 decoder and 16 input multiplexer

 

20. Late write SSRAM suffer with

(a) recovery time

(b) burst mode

(c) turn around penalty

(d) multi rate