DIC3

1. has extra inverters on its select inputs

(a) 74X139

(b) 74X129

(c) 74X130

(d) 74X119

 

2. For 74 × 138, 3 to 8 decoder 100000 input gives

(a) 10111110

(b) 11111100

(c) 11111110

(d) 11011110

 

3. The Boolean expression for output A0 of generic 8 input priority encoder in terms of intermediate variable H0 to

H7 is

(a) H1 + H2 + H5 + H7

(b) H1 + H3 + H5 + H7

(c) H1 + H3 + H5 + H6

(d) H0 + H3 + H5 + H7

 

4. must be asserted for any of its output to be asserted in 74 × 148

(a) EO H

(b) EI H

(c) EO L

(d) EI L

 

5. In 74 × 245, if G=0 and dir = 0 indicate

(a) transfer data from a source on bus A to a destination bus B

(b) trans receive depending on chip enable

(c) transfer data from a source on bus B to a destination bus A

(d) transfer data independently

6. General logic equation for multiplexer output: Iy is

(a)

N−1 Pj=0

EN.Mj.iDj

(b)

N−1 Pj=0

EN.Mi

(c)

N−1 Pj=0

EN.iDj

(d)

N−1 Pj=0

Mi.iDj

7. The square of three bit binary number A2A1A0 is represented as PQRSTU. Then Boolean expression for Q is

(a) A2(A11

A0 + A1 + A0)

(b) A2(A11

A10

+ A1A0)

(c) (A11

A10

_ A1A0)

(d) A2(A1A0)

 

8. is 8 bit comparator and has no cascading inputs.

(a) 74 × 153

(b) 74 × 138

(c) 74 × 682

(d) 74 × 85

 

9. The square of three bit binary number A2A1A0 is represented as PQRSTU. Then Boolean expression for S is

(a) (A11

A10

_ A1A0)

(b) (A11

A10

_ A1)

(c) A2A0 + A2A1

(d) A1A0

 

10. In 74 × 181, if S3 S2 S1 S0 = 0011, M = 1, then F is

(a) A _ B

(b) A1B

(c) A1B1

(d) A1 _ B

 

11. provide group carry look ahead outputs.

(a) 74 x 280

(b) 74 x 381

(c) 74 x 153

(d) 74 x 138

 

12. One of the following VHDL statement is used for Fixed point to floating point conversion

(a) if BV < 15 ,then M < = B (3down to 1); E < = “001“;

(b) if BV < 16 ,then M < = B (3down to 0); E < = “000“;

(c) if BV < 14 ,then M < = B (2down to 0); E < = “010“;

(d) if BV < 10 ,then M < = B (3down to 2); E < = “100“;

 

13. Important Flip Flop function for ASIC testing is

(a) scan capability

(b) switching capability

(c) input capability

(d) output capability

 

14. S - R latch characteristic equation is

(a) S1 + R1.Q

(b) Q_ = S + R1.Q

(c) S + R1.Q1

(d) S1 + R1.Q1

 

15. uses D latches.

(a) 74 × 174

(b) 74 × 74

(c) 74 × 112

(d) 74 × 373

 

16. is first generation sequential PLD.

(a) PAL16R8

(b) GAL16V8R

(c) PAL20L10

(d) PAL20L8

 

17. is up/down counter.

(a) 74 × 166

(b) 74 × 112

(c) 74 × 74

(d) 74 × 169

 

18. To get a flip - flop out of metastable state

(a) force the flip - flop into a unknown logic state using input signals

(b) force the flip - flop into a weak low logic state using input signals

(c) force the flip - flop into a valid logic state using input signals

(d) force the flip - flop into a weak high logic state using input signals

 

19. PROM (Bipolar technology) Read cycle is

(a) < 100ns

(b) 200ns

(c) 50 ms

(d) > 100ns

 

20. is 8K × 8 SRAM.

(a) HM6264

(b) 74HC04

(c) GAL22V10

(d) 2764