JNTU ONLINE EXAMINATIONS [Mid 2 - dica]

1. _ _ _ _ _ _ has extra inverters on its select inputs [01M02]
   1. 74X139
   2. 74X130
   3. 74X129
   4. 74X119
2. For 74X139 dual 2 to 4 decoder,011 input gives _ _ _ _ _ _ output. [01M03]
   1. 0111
   2. 1011
   3. 1111
   4. 1100
3. One of the following is dual 2 to 4 decoder [01S01]
   1. 74LS139
   2. 74X130
   3. 74X129
   4. 74X119
4. _ _ _ _ _ _ contains two independent or identical 2 to 4 decoders [01S02]
   1. 74X139
   2. 74X130
   3. 74X129
   4. 74X119
5. For _ _ _ _ _ _ , the outputs and enable input are active low. [01S03]
   1. 74X139
   2. 74X130
   3. 74X129
   4. 74X119
6. One of the following is 3 to 8 decoder [01S04]
   1. 74X138
   2. 74X130
   3. 74X119
   4. 74X36
7. 74 X 138 has [01S05]
   1. three enable inputs
   2. two enable inputs
   3. four enable inputs
   4. one enable input
8. 10011 input in seven segment decodes as _ _ _ _ _ _ _ _ _ output. [02D01]
   1. 1111001
   2. 1111101
   3. 1011001
   4. 1111000
9. If G1,G2A,G2B are enable inputs, C,B,A are inputs, then output Y₅ in terms of enable & input signal for 3 to 8 decoder is [02D02]
   1. G1. G2A. G2B.C.B^.
   2. G2A. G2B.C.B^.
   3. G1. G2A. G2B.C.B¹
   4. G1. G2A. G2B.B^.
10. For 74 X 138, 3 to 8 decoder 100000 input gives [02M01]
    1. 11111110
    2. 11111100
    3. 11011110
    4. 10111110
11. If I₀ to I₇ are inputs and Y₀ to Y₂ are outputs of 8 to 3 encoder, then Y₂ in terms of inputs is [02M02]
    1. 
    2. 
    3. 
    4. 
       
12. A seven segment decoder has _ _ _ _ _ _ _ _ as its input code [02S02]
    1. 4 bit BCD
    2. 6 bit excess 3
    3. 3 bit octal
    4. 3 bit hex
13. _ _ _ _ _ _ _ _ is seven segment decoder [02S03]
    1. 74X49
    2. 74X138
    3. 74X491
    4. 74X149
14. Blanking input in 74X49 is [02S04]
    1. Bi _ L
    2. Bi _ H
    3. B _ L
    4. Bi _ U
15. 10111 input gives _ _ _ _ _ _ _ _ _ _ _ output in seven segment decoder [02S05]
    1. 1110000
    2. 1110001
    3. 1110010
    4. 1100000
16. The 1 out of 2ⁿ coded outputs of n bit binary decoder used to control a set of [02S06]
    1. 2ⁿ devices
    2. devices
    3. devices
    4. 2 n devices
17. If ABCD represents naturally BCD, PQRST represents 2 out of 5 code, then T is [03D01]
    1. 
    2. 
    3. 
    4. 
18. 001111111 input produce _ _ _ _ _ _ _ _ in 74 X 148, 8 bit priority encoder. [03D02]
    1. 11101
    2. 11001
    3. 10101
    4. 11100
19. The Boolean expression for output A₀ of generic 8 input priority encoder in terms of intermediate variable H₀ to H₇ is [03M01]
    1. 
    2. 
    3. 
    4. 
20. If ABCD represents naturally BCD, PQRST represents 2 out of 5 code, then P is [03M02]
    1. 
    2. 
    3. 
    4. 
21. The Boolean expression for output A₂ of generic 8 input priority encoder in terms of intermediate variables H₀ to H₇ is [03M03]
    1. 
    2. 
    3. 
    4. 
22. 0XX011111 gives _ _ _ _ _ _ _ _ output in priority encoder [03M04]
    1. 10101
    2. 00101
    3. 10001
    4. 10100
23. The IDLE output in generic 8 input priority encoder is asserted if _ _ _ _ _ are asserted. [03S01]
    1. no inputs
    2. I1, I4
    3. I2,I6
    4. I4,I5
24. _ _ _ _ _ _ _ _ is a priority encoder [03S02]
    1. 74 X 148
    2. 74 X 146
    3. 74 X 48
    4. 74 X 144
25. 74 X 148 inputs are [03S03]
    1. active low
    2. active high
    3. inverted
    4. buffered & inverted
26. 74 X 148 outputs are [03S04]
    1. active low
    2. active high
    3. buffered
    4. inverted
27. _ _ _ _ _ _ _ must be asserted for any of its output to be asserted in 74 X 148 [04D01]
    1. EI _ L
    2. EO _ H
    3. EO _ L
    4. EI _ H
28. Shown in figure (a) represents Figure(a) [04M01]
    1. Inverting active low enable buffer
    2. Inverting active high enable buffer
    3. non Inverting active low enable buffer
    4. non Inverting active high enable buffer
29. Shown in figure (a) represents Figure(a) [04M02]
    1. Non - inverting active high enable buffer
    2. inverting active low enable buffer
    3. non Inverting active low enable buffer
    4. Inverting active high enable buffer
30. Shown in figure (a) represents Figure(a) [04M03]
    1. Non - inverting active low enable buffer
    2. inverting active low enable buffer
    3. non Inverting active high enable buffer
    4. Inverting active high enable buffer
31. Shown in figure (a) represents Figure(a) [04M04]
    1. Inverting active high enable buffer
    2. Non - inverting active low enable buffer
    3. inverting active low enable buffer
    4. Non - inverting active high enable buffer
32. EO _ L signal is an enable output designed to be connected to _ _ _ _ _ _ _ _ _ input of another 74 X148. [04S01]
    1. EI L
    2. EO H
    3. EO L
    4. EI H
33. _ _ _ _ _ _ _ _ _ _ is asserted when the device is enabled in 74 X 148. [04S02]
    1. GS L
    2. GO H
    3. GO L
    4. GS H
34. _ _ _ _ _ _ _ _ _ used to describe prioritization in VHDL. [04S03]
    1. if then else
    2. port
    3. assert
    4. while
35. The purpose of conv _ std _ logic _ vector (j, n) in VHDL coding of 74 X 148, 8 input priority encoder is to convert integer j to [04S04]
    1. std logic vector
    2. std logic
    3. real
    4. std ulogic
36. _ _ _ _ _ _ _ _ is enable input in 74 X 148 [04S05]
    1. EI L
    2. EI1 L
    3. EI1 H
    4. EI H
37. In 74 X 245, if G=0 and dir = 0 indicate [05D01]
    1. transfer data from a source on bus B to a destination bus A
    2. transfer data from a source on bus A to a destination bus B
    3. transfer data independently
    4. trans receive depending on chip enable
38. _ _ _ _ _ _ _ _ must be asserted to enable devices three state outputs in three state buffer [05M01]
    1. G1 L, G2 L
    2. G2 H, G3 L
    3. G1 L, G3 H
    4. G1 H, G3 L
39. 74 X 541 input has _ _ _ _ _ _ of hysteris [05M02]
    1. 0.4 V
    2. 0.6V
    3. 0.8V
    4. 0.3V
40. _ _ _ _ _ _ _ _ _ _ contains four independent Non - inverting three state buffer. [05S01]
    1. 74 X 126
    2. 74 X 120
    3. 74 X 129
    4. 74 X 136
41. _ _ _ _ _ _ _ _ _ _ contains four independent Non - inverting three state buffer. [05S02]
    1. 74 X 125
    2. 74 X 135
    3. 74 X 146
    4. 74 X 136
42. _ _ _ _ _ _ _ _ _ _ is octal Non - inverting three state buffer [05S03]
    1. 74 X 541
    2. 74 X 546
    3. 74 X 451
    4. 74 X 544
43. number of don't care inputs in a BCD adder (consider 9 inputs BCD adder) is [05S04]
    1. 312
    2. 214
    3. 412
    4. 300
44. _ _ _ _ _ _ _ _ _ is octal three state Trans receiver [05S05]
    1. 74 X 245
    2. 74 X 254
    3. 74 X 243
    4. 74 X 241
45. _ _ _ _ _ _ _ _ _ _ _ contains inverting buffer [05S06]
    1. 74540
    2. 74542
    3. 74543
    4. 74504
46. _ _ _ _ _ _ _ _ _ in 74 X 245 determines direction of transfer [05S07]
    1. dir
    2. G1 L
    3. G2 L
    4. G L
47. General logic equation for multiplexer output: I_y is [06D01]
    1. 
    2. 
    3. 
    4. 
48. In 74 X 245, if G=0 and dir = 1 indicate [06M01]
    1. transfer data from a source on bus A to a destination bus B
    2. transfer data from a source on bus B to a destination bus A
    3. transfer data independently
    4. trans receive independently depending Al also
49. In 74X245 , if G=1 and dir = X indicate [06M02]
    1. transfers data on busses A & B independently
    2. transfer data from a source on bus A to a destination bus B
    3. transfer data from a source on bus B to a destination bus
    4. trans receive independently A or B
50. If _ _ _ _ _ _ _ _ _ _ _ is asserted, then three state buffer for selected direction is enabled in 74 X 245 [06S01]
    1. G L
    2. G1 L
    3. G2 L
    4. dir
51. _ _ _ _ _ _ _ _ _ used between two bi-directional busses [06S02]
    1. 74 X 245
    2. 74 X 541
    3. 74 X 151
    4. 74 X 148
52. _ _ _ _ _ _ _ _ _ _ contains pairs of three state buffers connected in opposite directions between each pair of pins, so data can be transferred in either direction. [06S03]
    1. bus trans receiver
    2. asynchronous bus receiver
    3. synchronous bus transmitter
    4. programmable interface
53. _ _ _ _ _ _ _ _ _ _ _ is a 8 input 1 bit multiplexer [06S04]
    1. 74 X 151
    2. 74 X 541
    3. 74 X 155
    4. 74 X 148
54. For 74 X 151, input 0001 produces [06S05]
    1. D1 & D1¹
    2. D1 & D2¹
    3. D5 & D5¹
    4. D5 & D6¹
55. For 74 X 151, input 0101 produces [06S06]
    1. D5 & D5¹
    2. D1 & D1¹
    3. D5 & D6¹
    4. D1 & D2¹
56. _ _ _ _ _ _ _ _ _ _ _ is 2 input, 4 bit multiplexer. [06S07]
    1. 74 X 157
    2. 74 X 541
    3. 74 X 155
    4. 74 X 148
57. The square of three bit binary number is represented as PQRSTU. Then Boolean expression for R is [07D01]
    1. 
    2. 
    3. 
    4. 
58. The square of three bit binary number is represented as PQRSTU. Then Boolean expression for Q is [07D02]
    1. 
    2. )
    3. 
    4. )
59. Three state outputs in multiplexer useful when [07M01]
    1. n input multiplexers are combined to form larger multiplexer.
    2. n -1 input multiplexers are combined to form larger multiplexer
    3. n input multiplexers are combined to form larger demultiplexer
    4. n -1 input multiplexers are combined to form larger demultiplexer
60. 32 input, 1 bit multiplexer contains [07M02]
    1. 74 X 139, four 74 X 151
    2. 74 X 136, two 74 X 151
    3. 74 X 131, four 74 X 155
    4. 74 X 130, four 74 X 159
61. If ABCD represents naturally BCD, PQRST represents 2 out of 5 code, then R is [07M03]
    1. 
    2. AD + CD + BC¹
    3. 
    4. 
62. ABCD are four naturally BCD digits, the Boolean expression for combinational logic circuit which detect numbers that are greater than or equal to 7 is [07M04]
    1. A + BCD
    2. [A + BCD]¹
    3. A + BC+D
    4. A + B+CD
63. _ _ _ _ _ _ _ _ _ _ is 4 input , 2 bit multiplexer [07S01]
    1. 74 X 153
    2. 74 X 151
    3. 74 X 541
    4. 74 X 148
64. _ _ _ _ _ _ _ _ _ _ has three state outputs. [07S02]
    1. 74 X 251
    2. 74 X 153
    3. 74 X 541
    4. 74 X 148
65. _ _ _ _ _ _ used as 1 bit 8 output demultiplexer. [07S03]
    1. 74 X 138
    2. 74 X 251
    3. 74 X 153
    4. 74 X 541
66. _ _ _ _ _ _ is 9 bit parity generator. [07S04]
    1. 74 X 280
    2. 74 X 86
    3. 74 X 138
    4. 74 X 153
67. The square of three bit binary number is represented as PQRSTU. Then Boolean expression for U is [08D01]
    1. A₀
    2. 
    3. 
    4. 
68. The square of three bit binary number is represented as PQRSTU. Then Boolean expression for P is [08D02]
    1. 
    2. 
    3. 
    4. 
69. AGTBout in 74 X 85 is equal to [08M01]
    1. 
    2. 
    3. 
    4. 
70. AEQB out in 74 X 85 is equal to [08M02]
    1. 
    2. 
    3. 
    4. 
71. ALTB out in 74 X 85 is equal to [08M03]
    1. 
    2. 
    3. 
    4. 
72. A block of flats has four floors and it is arranged that the lights for the stair well can be switched on or off at any floor level.When the switch on, that level is operated. If switches on the four levels A, B ,C, & D and lights L ,the Boolean expression for L is [08M04]
    1. A oplu; B oplus C oplus D
    2. A oplus B oplus C D
    3. A oplus B C oplus D
    4. A B oplus C oplus D
73. _ _ _ _ _ _ _ _ used to check the parity bit when a code word is received. [08S01]
    1. 74 X 280
    2. 74 X 86
    3. 74 X 138
    4. 74 X 153
74. _ _ _ _ _ _ _ _ is 4 bit comparator. [08S02]
    1. 74 X 85
    2. 74 X 280
    3. 74 X 138
    4. 74 X 153
75. _ _ _ _ _ _ _ _ has cascading inputs for combining multiple '85s to create comparator for more than four bits. [08S03]
    1. 74 X 85
    2. 74 X 280
    3. 74 X 138
    4. 74 X 153
76. _ _ _ _ _ _ _ _ is 8 bit comparator and has no cascading inputs. [08S04]
    1. 74 X 682
    2. 74 X 85
    3. 74 X 138
    4. 74 X 153
77. The square of three bit binary number is represented as PQRSTU. Then Boolean expression for S is [09D01]
    1. 
    2. 
    3. )
    4. )
78. If the five bit number is ABCDE, the Boolean expression for majority logic function M is ( M = 1, when the majority of digits in a five bit number are 1) [09D02]
    1. A( B+ E) (C + D) + BE ( A+ C+ D) + CD ( A+ B+ E)
    2. A( B+ E) (C + D) + BE ( A+ C+ D) + ( A+ B+ E)
    3. ( B+ E) (C + D) + E ( A+ C+ D) + CD ( A+ B+ E)
    4. A( B+ E) (C + D) + B ( A+ C+ D) + C ( A+ B+ E)
79. If A, B, Bin are inputs and D & Bout are outputs of full sub tractor, then B out is [09M01]
    1. 
    2. 
    3. 
    4. 
80. Parity checking function for even parity is [09M02]
    1. 
    2. 
    3. 
    4. 
81. Parity checking function F₀ for odd parity is [09M03]
    1. [D_2 oplus D_1 oplus D_0 oplus P_0]¹
    2. 
    3. 
    4. 
82. If and D₀ are three bit input to parity generator, then P_e is even parity bit. Boolean expression for P_e in terms of is [09S01]
    1. 
    2. 
    3. 
    4. 
83. If and D₀ are three bit input to parity generator, then P_o is odd parity bit. Boolean expression for P_o in terms of is [09S02]
    1. (D_2 oplus D_1 oplus D_0)¹
    2. 
    3. 
    4. (D_2 oplus D_1 + D_0 )¹
84. if then else VHDL statement used within [09S03]
    1. process
    2. WHILE
    3. select
    4. assert
85. If the input & output signal voltage levels(L & H) are indicated in truth table, then it is also known as [09S04]
    1. function table
    2. excitation table
    3. state table
    4. state diagram
86. _ _ _ _ _ _ _ _ _ _ _ is quadruple 2 input XOR gate. [09S05]
    1. 74 X 86
    2. 74 X 280
    3. 74 X 138
    4. 74 X 153
87. Total worst case delay in ripple adder is [10D01]
    1. 
    2. 
    3. 
    4. 
88. For carry look ahead adder inputs), then is [10M01]
    1. 
    2. 
    3. 
    4. 
89. In 74 X 283, carry is [10M02]
    1. 
    2. 
    3. 
    4. 
90. The VHDL code for difference bit in full sub tractor is [10S01]
    1. diff <= x XOR Y XOR ;
    2. ;
    3. ;
    4. ;
91. Borrow out in full sub tractor VHDL code is [10S02]
    1. bout < = ( not X and or ( not X and Y) or ( and Y);
    2. bout < = ( not X n and ) or ( not X and y) nor ( and Y);
    3. bout < = ( not X and ) nor ( not X nand y) or ( and Y);
    4. bout < = ( not X and ) nor ( not X and y) or ( nand Y);
92. For more flexible comparisions & arithmetic operations IEEE 1076-3 created a package. it is [10S03]
    1. std logic arith
    2. std logic ulogic
    3. std logic 1164
    4. std logic unsigned
93. _ _ _ _ _ _ _ _ _ is a 4 bit binary adder. [10S04]
    1. 74 X 283
    2. 74 X 280
    3. 74 X 138
    4. 74 X 153
94. Total propagation delay from C₀ to in 16 bit group ripple adder using 74 X 283 is [10S05]
    1. same as that of eight inverting gates.
    2. twice the eight inverting gates
    3. same as that of six inverting gates
    4. same as that of four inverting gates
95. _ _ _ _ _ _ _ _ is 4 bit ALU. [10S06]
    1. 74 X 181
    2. 74 X 280
    3. 74 X 138
    4. 74 X 153
96. In , if S3 S2 S1 S0 = 0011, M = 1, then F is [10S07]
    1. A
    2. 
    3. 
    4. 
97. For 74 x 182, is [11D01]
    1. 
    2. 
    3. 
    4. 
98. For 74 x 382, if S2 S1 S0 =110, then F is [11M01]
    1. 
    2. 
    3. 
    4. 
99. In 24 bit comparator circuit PGTQ is [11M02]
    1. GT2+EQ2 . GT1 + EQ2. EQ1 . GT0
    2. 
    3. 
    4. 
100. In 74 x 181, if S3 S2 S1 S0 = 1100, M = 1, then F is [11S01]
     1. 0000
     2. 1010
     3. 1111
     4. 1001
101. _ _ _ _ _ _ _ provide group carry look ahead outputs. [11S02]
     1. 74 × 381
     2. 74 × 280
     3. 74 × 138
     4. 74 × 153
102. For _ _ _ _ _ _ _ _ , if S2 S1 S0 = 100 then function output ,F is [11S03]
     1. 74 × 381
     2. 74 × 280
     3. 74 × 138
     4. 74 × 153
103. _ _ _ _ _ _ _ _ _ multiplier use a single adder & a register to accumulate the partial products. [11S04]
     1. sequential
     2. Carry save
     3. group ripple
     4. Parity
104. _ _ _ _ _ _ _ _ specify the direction of shift, type of shift and amount of shift. [11S05]
     1. Barrel shifter
     2. Carry save shifter
     3. sequential shifter
     4. group ripple shifter
105. If barrel shifter uses _ _ _ _ _ _ _ ,the data delay will be 1. [11S06]
     1. 74 × 251
     2. 74 × 280
     3. 74 × 138
     4. 74 × 182
106. First and second highest priority encoder circuit uses [12D01]
     1. two 74LS148, one 74LS138, 74LS04, 74LS00
     2. four 74LS148, four 74LS138, two74LS04,74LS00
     3. three 74LS148, one 74LS138, four74LS04, two74LS00
     4. one 74LS148, one 74LS138,two74LS04, three74LS00
107. 24 bit comparator uses [12D02]
     1. three 74 × 682, two 74 × 27, three 74 × 02
     2. two 74 × 682, two 74 × 29, two 74 × 03
     3. four 74 × 684, three74 × 27, three 74 × 02
     4. three 74 × 682, one 74 × 27, two 74 × 02
108. One of the following VHDL statement is used for for Dual parity encoder [12D03]
     1. if R(i) = `1' and Avalid = `0', then
        A <= conv _ std _ logic _ vector (i, 3); Avalid < = `1 ';
        elsif R(i) = `1' and Bvalid = `0', then
        B < = conv _ std _ logic _ vector (i,3); Bvalid < = `1';
        end if;
     2. if R(i) = `1' and Avalid =0, then
        A <= conv _ std _ logic _ vector (i, 3); Avalid < = `1'; end if;
     3. if R(i) = `1' and Bvalid = `0', then
        B < = conv _ std _ logic _ vector (i,3); Bvalid < = `1';
        end if;
     4. if R(i) = `1' and Avalid =1, then
        A < = conv _ std _ logic _ vector (i, 3); Avalid < = `0';
        Elsif R(i) = `0' and Bvalid = `0', then
        B < = conv _ std _ logic _ vector (i,3); Bvalid < = �0�; end if;
109. If B is 11 bit unsigned binary integer & M,E are 4 bits and 3 bits ( 7 point floating Point number), T is truncation error, then B is [12M01]
     1. 
     2. 
     3. 
     4. 
110. In 24 bit comparator circuit, PEQQ is [12M02]
     1. EQ2.EQ1.EQ0
     2. 
     3. 
     4. 
111. Mode dependent comparator circuit uses [12M03]
     1. one 74LS682, one74 × 86 and two 74 × 157.
     2. two 74LS689, one74 × 86 and one74 × 157.
     3. three 74LS682, one74 × 86 and two 74 × 159.
     4. one 74LS682, two74 × 89 and FOUR 74 × 157.
112. One of the following VHDL statement is used for left rotate in 6 function barrel shifter [12M04]
     1. 
     2. 
     3. 
     4. 
113. A combinational fixed point to floating point encoder consists of [12S01]
     1. one 74 × 148, three 74 × 154
     2. one 74 × 148, two 74 × 154, 74 × 251
     3. two 74 × 154, 74 × 251
     4. 74 × 280,two 74 × 138
114. One of the following VHDL statement is used for Fixed point to floating point conversion [12S02]
     1. if BV <>
     2. if BV <>
     3. if BV <>
     4. if BV <>
115. 74x682 does not provide [12S03]
     1. less than output
     2. greater than output
     3. equal output
     4. output
116. 74LS109 has the following characteristic equation. [13D01]
     1. 
     2. 
     3. 
     4. 
117. 74LS74 characteristic equation is [13M01]
     1. 
     2. 
     3. 
     4. 
118. In JK master slave FF, because of the gating on master latches S & R inputs, FF output change to1 even though K and not J is asserted at the end of the Triggering pulse.This behaviour known as [13M02]
     1. 1's latching
     2. 0s latching
     3. don't care latching
     4. Z latching
119. _ _ _ _ _ _ _ _ _ is the minimum delay between negative S & R( in S - R latch) for them to be considered non simultaneous. [13S01]
     1. Recovery time
     2. propagation time
     3. delay time
     4. access time
120. Commercial TTL positive edge triggered D flipflop do not use [13S02]
     1. master slave latch design
     2. master latch design
     3. synchronous latch design
     4. asynchronous latch design
121. _ _ _ _ _ _ _ _ _ _ is positive edge triggering D FlipFlop. [13S03]
     1. 74LS74
     2. 74LS109
     3. 74LS79
     4. 74LS70
122. Important Flip Flop function for ASIC testing is [13S04]
     1. scan capability
     2. input capability
     3. output capability
     4. switching capability
123. Figure (a) represents Figure(a) [13S05]
     1. positive edge triggered D Flip Flop with scan.
     2. positive edge triggered D Flip Flop
     3. negative edge triggered D Flip Flop with scan.
     4. negative edge triggered D Flip Flop
124. Flip Flops with postponed output indicator (Master - slave S R FF) are called [13S06]
     1. pulse triggered Flip Flop
     2. positive edge triggered D Flip Flop with scan
     3. negative edge triggered T Flip Flop with scan.
     4. negative edge triggered JK Flip Flop with scan.
125. _ _ _ _ _ _ _ _ is a TTL positive edge trigger JKFF with active low K input. [13S07]
     1. 74 X 109
     2. 74LS74
     3. 74 X 190
     4. 74 X 10
126. Set up time margin is [14D01]
     1. 
     2. 
     3. 
     4. 
127. Hold time margin is [14D02]
     1. 
     2. 
     3. 
     4. 
128. For proper circuit operation [14D03]
     1. 
     2. 
     3. 
     4. 
129. If _ _ _ _ _ _ _ _ _ _ _ is negative, the circuit don't work. [14M01]
     1. set up time margin
     2. Hold time margin
     3. 
     4. 
130. The sum of minimum values of and must be [14M02]
     1. greater than
     2. greater than
     3. less than
     4. less than Set up time margin
131. S - R latch characteristic equation is [14S01]
     1. 
     2. 
     3. 
     4. 
132. D FF with enable characteristic equation is [14S02]
     1. 
     2. 
     3. 
     4. 
133. T FF with enable characteristic equation is [14S03]
     1. 
     2. 
     3. 
     4. 
134. VHDL statement for positive edge triggered D FF is [14S04]
     1. Q < = D when clk' event and clk =`1' else Q;
     2. Q < = D when clk' event and clk = `0' else not Q ;
     3. Q < = not D when clk' event and clk = `1' else Q;
     4. Q > = D when clk' event and clk =`0' else not Q;
135. _ _ _ _ _ _ _ _ contain four D latches. [14S05]
     1. 74 X 375
     2. 74 X 74
     3. 74 X 112
     4. 74 X 175
136. In 74 X175, _ _ _ _ _ _ _ _ _ _ _ are buffered. [15D01]
     1. clock and CLR _ L
     2. clock, D
     3. CLR, Q
     4. 1^Q
137. consider Bus holder circuit in 3.3V CMOS LVC. Specify a maximum over ride cutoff [15M01]
     1. 500 μ A
     2. 100 mA
     3. 300micro A
     4. 200 micro A
138. If no output is driving the bus, it will float. So an active _ _ _ _ _ _ _ _ _ _ is used to pull a floating bus to a valid high logic level [15M02]
     1. Bus holder circuit
     2. SSRAM
     3. SDRAM
     4. miller circuit
139. _ _ _ _ _ _ _ _ _ _ is JKFF with active low clock input. [15S01]
     1. 74 × 112
     2. 74 × 74
     3. 74 × 375
     4. 74 × 175
140. _ _ _ _ _ _ _ _ _ _ contains 4 bit register with a common clock and asynchronous clear input. [15S02]
     1. 74 × 175
     2. 74 × 375
     3. 74 × 370
     4. 74 × 112
141. _ _ _ _ _ _ _ _ _ _ is 6 bit register. [15S03]
     1. 74 × 174
     2. 74 × 375
     3. 74 × 75
     4. 74 × 112
142. _ _ _ _ _ _ _ _ _ _ is ( octal edge trigger D FF) 8 bit register. [15S04]
     1. 74 × 374
     2. 74 × 174
     3. 74 × 74
     4. 74 × 112
143. _ _ _ _ _ _ _ _ _ _ uses D latches. [15S05]
     1. 74 × 373
     2. 74 × 174
     3. 74 × 74
     4. 74 × 112
144. _ _ _ _ _ _ _ _ _ _ _ _ uses pin 1 for asynchronous clear input. [15S06]
     1. 74 × 273
     2. 74 × 174
     3. 74 × 74
     4. 74 × 112
145. _ _ _ _ _ _ _ _ _ _ _ _ uses pin1 for active low clock enable input. [15S07]
     1. 74 × 377
     2. 74 × 174
     3. 74 × 74
     4. 74 × 112
146. GAL22V10 has = [16M01]
     1. 13 or 2.5
     2. 10 or 1.5
     3. 5 or 20
     4. 12 or 3.5
147. Little rectangular symbols inside the buffer symbols indicate [16S01]
     1. Hysterisis
     2. inverter
     3. amplification
     4. inductance
148. _ _ _ _ _ _ _ _ _ _ _ _ is first generation sequential PLD. [16S02]
     1. PAL16R8
     2. PAL20L8
     3. PAL20L10
     4. GAL16V8R
149. _ _ _ _ _ _ _ _ _ has `0' registered outputs. [16S03]
     1. PAL20L8
     2. PAL16R8
     3. GAL16V8R
     4. GAL22V10
150. _ _ _ _ _ _ _ _ _ _ _ _ is electrically erasable PLD. [16S04]
     1. GAL16V8
     2. PAL16R8
     3. PAL20L8
     4. GA2V10
151. In _ _ _ _ _ _ _ _ _ _ ,output logic macro cell individually configured to bypass flip flop [16S05]
     1. GAL16V8R
     2. PAL20L8
     3. PAL16R8
     4. GAL22V10
152. The macro cells in PAL16V8R can be [16S06]
     1. registered and combinational
     2. sequential and combinational
     3. registered and sequential
     4. sequential and buffered, inverted
153. _ _ _ _ _ _ _ _ _ _ _ in PLD represents the propagation delay from rising edge of clock to primary output. [16S07]
     1. 
     2. 
     3. 
     4. t_H
154. _ _ _ _ _ _ _ _ _ _ _ _ _ is a synchronous 4 bit binary counter with active low load and clear input. [16S08]
     1. 74 × 163
     2. 74 × 160
     3. 74 × 74
     4. 74 × 112
155. _ _ _ _ _ _ _ _ _ _ is a modulo 10 counter. [16S09]
     1. 74 × 160
     2. 74 × 166
     3. 74 × 74
     4. 74 × 112
156. In 74 X 299, bits shifted right if [17M01]
     1. S1 =0 , SD =1
     2. S1 =0 , SD =0
     3. S1 =1 , SD =1
     4. S1 =1, SD =0
157. In serial to parallel conversion using parallel out shift register, the following ICs are used. [17M02]
     1. two 74 X163, one 74 X 164, two 74 X 04, one 74 X 27, one 74 X 377
     2. threee 74 X 163, one 74 X 164, two 74 X 04, two74 X 27, one 74 X 377.
     3. two 74 X 163, one 74 X 164, three 74 X 04, one 74 X 27, two74 X 377.
     4. two 74 X 163, four74 X 164, three 74 X 04, one 74 X 27, one 74 X 377.
158. LFSR also known as [17M03]
     1. maximum length sequence generator
     2. minimum length sequence generator
     3. shift circular register
     4. Johnson counter
159. _ _ _ _ _ _ _ _ _ _ _ is up/down counter. [17S01]
     1. 74 X 169
     2. 74 X 166
     3. 74 X 74
     4. 74 X 112
160. one of the follwing VHDL statement used for upcounter is [17S02]
     1. 
     2. 
     3. 
     4. 
161. _ _ _ _ _ _ _ _ _ _ _ is 8 bit serial in parallel out shift register. [17S03]
     1. 74 X 164
     2. GAL22V10
     3. 74 X 74
     4. 74 X 112
162. _ _ _ _ _ _ _ _ _ _ _ is 8 bit parallel in serial out shift register. [17S04]
     1. 74166
     2. GAL22V10
     3. 74 X 74
     4. 74 X 112
163. _ _ _ _ _ _ _ _ _ _ _ is universal shift register. [17S05]
     1. 74 X 194
     2. 74 X 166
     3. 74 X 74
     4. 74 X 112
164. In ring counter using 74 X 194, LIN serial input connected to [17S06]
     1. QA
     2. QA¹
     3. CLR L
     4. TE
165. In Johnson counter using 74 X 194 , LIN serial input connected to [17S07]
     1. QA¹
     2. QA
     3. CLR L
     4. TE
166. For proper synchronous operation, one of the following is considered [18D01]
     1. 
     2. 
     3. 
     4. 
167. Metastability resolution time, t_r is [18D02]
     1. 
     2. 
     3. 
     4. 
168. MTBF (t_r) is [18G03]
     1. 
     2. 
     3. [erfc( t_r / τ) ] / [ T_0 .f .a
     4. 
169. To get a flip - flop out of metastable state [18M01]
     1. force the flip - flop into a valid logic state using input signals
     2. force the flip - flop into a weak high logic state using input signals
     3. force the flip - flop into a weak low logic state using input signals
     4. force the flip - flop into a unknown logic state using input signals
170. one of the following VHDL statement used for shift circular register circuit [18S01]
     1. ( 7 down to 1);
     2. ( 6 down to 1);
     3. ( 6 down to 0);
     4. ( 5 down to 1);
171. For reliable synchronous design, one of the following is valid. [18S02]
     1. ensure FF have positive set up & hold time margins
     2. synchronizers should have medium probability of failure
     3. maximize amount of clock skew
     4. ensure FF have negative set up & hold time margins
172. _ _ _ _ _ _ _ _ _ _ _ structure eliminate clock skew in ASIC. [18S03]
     1. clock tree
     2. synchronizers
     3. equalizers
     4. clock latency
173. A method of gating the clock that generates only minimal clock skew is [18S04]
     1. gates in same IC package is used to generate un gated clock and gated clocks from same master clock signal.
     2. gates in different IC package is used to generate ungated clock and gated clocks from same master clock signal.
     3. gates in same IC package is used to generate ungated clock and gated clocks from different master clock signal.
     4. using of equalizers and digital delay lines
174. For reliable synchronous design , one of the following is valid. [18S05]
     1. minimize amount of clock skew
     2. synchronizers should have medium probability of failure
     3. ensure FF have negative set up & hold time marging
     4. maximize amount of clock skew
175. For reliable synchronous design , one of the following is valid. [18S06]
     1. synchronizers should have low probability of failure.
     2. synchronizers should have medium probability of failure.
     3. ensure FF have negative set up & hold time marging
     4. maximize amount of clock skew
176. EPROM (CMOS Technology) Write cycle is [19D01]
     1. 10 - 50 μs/byte
     2. 50 - 100 μs /byte
     3. 70 - 500 μs /byte
     4. 100 - 500 μs /byte
177. Two dimensional decoding allows a 128 X 1 ROM to be built with [19M01]
     1. 3 to 8 decoder and 16 input multiplexer
     2. 2 to 4 decoder and 10 input multiplexer
     3. 3 to 10 decoder and 20 input multiplexer
     4. 10 to 1024 decoder and 1024 input multiplexer
178. A 1M X 1 ROM could be built with [19M02]
     1. 10 to 1024 decoder and 1024 input multiplexer
     2. 3 to 8 decoder and 16 input multiplexer
     3. floating source MOS
     4. 3 to 10 decoder and 20 input multiplexer
179. For 74HC04, low level is [19S01]
     1. 
     2. = 1.35 V
     3. 
     4. 
180. _ _ _ _ _ _ _ _ _ _ _ is used to reduce the decoder size in ROM [19S02]
     1. Two dimensional decoding
     2. one dimensional decoding
     3. five dimensional decoding
     4. four dimensional decoding
181. PROM (Bipolar technology) Read cycle is [19S03]
     1. 
     2. 200ns
     3. 
     4. 50 ms
182. EEPROM ( NMOS Technology) Read cycle is [19S04]
     1. 50 - 200 ns
     2. 250 -1 200ms
     3. 250 - 300ns
     4. 500 - 1500ns
183. EPROMs will have [19S05]
     1. floating gate MOS
     2. floating source MOS
     3. floating drain MOS
     4. floating body MOS
184. _ _ _ _ _ _ _ _ _ _ is 8K X 8 EPROM. [19S06]
     1. 2764
     2. HM6264
     3. 74 X 74
     4. 74 X 112
185. _ _ _ _ _ _ _ _ _ _ _ input must be asserted to enable outputs in EPROM. [19S07]
     1. output enable(OE)
     2. CLR L
     3. WE L
     4. CS
186. In SRAMs output buffer is automatically disabled whenever _ _ _ _ _ _ _ _ is asserted ,even if OE _ L is asserted. [20D01]
     1. WE L
     2. WE H
     3. CLR L
     4. CLR H
187. Shown in figure (a) represents Figure(a) [20D02]
     1. storage cell for one bit in a DRAM
     2. storage cell for one byte in a EPROM
     3. storage cell for two bit in a SSRAM
     4. storage cell for two bit in a EEPROM
188. Shown in figure (a) represents Figure(a) [20G01]
     1. digital attenuator
     2. modem
     3. codec
     4. PCM transmitter
189. _ _ _ _ _ _ _ _ _ is the 8 bit companded encoding. [20S01]
     1. μ law PCM
     2. QAM
     3. DPCM
     4. PWM
190. _ _ _ _ _ _ _ _ is 8K X 8 SRAM. [20S02]
     1. HM6264
     2. GAL22V10
     3. 2764
     4. 74HC04
191. _ _ _ _ _ _ _ _ _ _ _ adds OUTREG to the read data path. [20S03]
     1. A ZBT SSRAM with pipelined outputs
     2. Extended data out DRAM
     3. Late write SSRAM
     4. EEPROM
192. Late write SSRAM suffer with _ _ _ _ _ _ _ _ [20S04]
     1. turn around penalty
     2. burst mode
     3. multi rate
     4. recovery time
193. _ _ _ _ _ _ _ _ _ _ _ _ supports burst mode. [20S05]
     1. late write SSRAM with flow through outputs
     2. Extended data out DRAM
     3. SRAMs output buffer
     4. ZBT SSRAM with pipelined outputs
194. _ _ _ _ _ _ _ _ _ contains separate OE L control input. [20S06]
     1. Extended data out DRAM
     2. SDRAM
     3. SSRAM
     4. LATE WRITE SSRAM
195. RAS to CAS delay is known as [20S07]
     1. CAS latency
     2. RAS latency
     3. CAS propagation time
     4. RAS recovery time