DIC9

1. One of the following is 3 to 8 decoder

(a) 74X138

(b) 74X130

(c) 74X36

(d) 74X119

 

2. If I0 to I7 are inputs and Y0 to Y2 are outputs of 8 to 3 encoder, then Y2 in terms of inputs is

(a) I4 + I5 + I6 + I1

(b) I4 + I3 + I6 + I7

(c) I4 + I5 + I6 + I7

(d) I4 + I5 + I2 + I7

 

3. 0XX011111 gives output in priority encoder

(a) 10001

(b) 10101

(c) 00101

(d) 10100

 

4. Shown in figure 4 represents

Figure 4

(a) Inverting active high enable buffer

(b) non Inverting active high enable buffer

(c) Non - inverting active low enable buffer

(d) inverting active low enable buffer

 

5. 74 × 541 input has of hysteris

(a) 0.8V

(b) 0.3V

(c) 0.6V

(d) 0.4 V

 

6. General logic equation for multiplexer output: Iy is

(a)

N−1 Pj=0

EN.Mj.iDj

(b)

N−1 Pj=0

EN.iDj

(c)

N−1 Pj=0

EN.Mi

(d)

N−1 Pj=0

Mi.iDj

7. The square of three bit binary number A2A1A0 is represented as PQRSTU. Then Boolean expression for Q is

(a) (A11

A10

_ A1A0)

(b) A2(A1A0)

(c) A2(A11

A0 + A1 + A0)

(d) A2(A11

A10

+ A1A0)

 

8. The square of three bit binary number A2A1A0 is represented as PQRSTU. Then

Boolean expression for P is

(a) A2A0 _ A2A1

(b) A2A0 + A2A1

(c) A2A0 + A2 _ A1

(d) A2A0 + A2A1A0

 

9. The square of three bit binary number A2A1A0 is represented as PQRSTU. Then Boolean expression for S is

(a) A2A0 + A2A1

(b) (A11

A10

_ A1A0)

(c) (A11

A10

_ A1)

(d) A1A0

 

10. is 4 bit ALU.

(a) 74 × 280

(b) 74 × 153

(c) 74 × 138

(d) 74 × 181

 

11. For 74 x 182, Ci+1 is

(a) (xiyi+xi+yi)(xiyi+Ci)

(b) (xiyi+xi+yi) _ (xi+yi+Ci)

(c) (xi+yi+xi+yi)(xiyi _ Ci)

(d) (xi+yi+xi+yi)(xi+yi+Ci)

 

12. One of the following VHDL statement is used for Fixed point to floating point conversion

(a) if BV < 14 ,then M < = B (2down to 0); E < = “010“;

(b) if BV < 16 ,then M < = B (3down to 0); E < = “000“;

(c) if BV < 15 ,then M < = B (3down to 1); E < = “001“;

(d) if BV < 10 ,then M < = B (3down to 2); E < = “100“;

 

13. is a TTL positive edge trigger JKFF with active low K input.

(a) 74 × 190

(b) 74 × 109

(c) 74 × 10

(d) 74LS74

 

14. S - R latch characteristic equation is

(a) S + R1.Q1

(b) Q_ = S + R1.Q

(c) S1 + R1.Q

(d) S1 + R1.Q1

 

15. is ( octal edge trigger D FF) 8 bit register.

(a) 74 × 74

(b) 74 × 112

(c) 74 × 374

(d) 74 × 174

 

16. Little rectangular symbols inside the buffer symbols indicate

(a) amplification

(b) inverter

(c) inductance

(d) Hysterisis

 

17. In ring counter using 74 × 194, LIN serial input connected to

(a) CLR L

(b) TE

(c) QA

(d) QA1

 

18. A method of gating the clock that generates only minimal clock skew is

(a) gates in different IC package is used to generate ungated clock and gated clocks from same master clock signal.

(b) using of equalizers and digital delay lines

(c) gates in same IC package is used to generate ungated clock and gated clocks from different master clock signal.

(d) gates in same IC package is used to generate un gated clock and gated clocks from same master clock signal.

 

19. For 74HC04, low level is

(a) < 1.5V

(b) < 1.35V

(c) > 1.35V

(d) = 1.35 V

 

20. contains separate OE L control input.

(a) Extended data out DRAM

(b) SSRAM

(c) SDRAM

(d) LATE WRITE SSRAMb