DIC 2

1. 74 × 138 has

(a) one enable input

(b) two enable inputs

(c) three enable inputs

(d) four enable inputs

 

2. 10011 input in seven segment decodes as output.

(a) 1111101

(b) 1011001

(c) 1111001

(d) 1111000

 

3. The IDLE output in generic 8 input priority encoder is asserted if are asserted.

(a) I4,I5

(b) I1, I4

(c) I2,I6

(d) no inputs

 

4. used to describe prioritization in VHDL.

(a) port

(b) assert

(c) if then else

(d) while

 

5. is octal Non - inverting three state buffer

(a) 74 × 541

(b) 74 × 544

(c) 74 × 451

(d) 74 × 546

 

6. For 74 × 151, input 0101 produces

(a) D1&D11

(b) D5&D61

(c) D1&D21

(d) D5&D51

 

7. is 9 bit parity generator.

(a) 74 × 138

(b) 74 × 153

(c) 74 × 280

(d) 74 × 86

 

8. used to check the parity bit when a code word is received.

(a) 74 × 153

(b) 74 × 86

(c) 74 × 280

(d) 74 × 138

 

9. is quadruple 2 input XOR gate.

(a) 74 × 138

(b) 74 × 86

(c) 74 × 153

(d) 74 × 280

 

10. The VHDL code for difference bit in full sub tractor is

(a) diff <= xNANDY ORbin;

(b) diff <= xXNORY XORbin;

(c) diff <= x XOR Y XOR bin ;

(d) diff <= xXNORY ORbin;

 

11. For 74 x 382, if S2 S1 S0 =110, then F is

(a) A · B

(b) A1B1

(c) A _ B

(d) A1 _ B

 

12. 74x682 does not provide

(a) greater than output

(b) equal output

(c) less than output

(d) output

 

13. In JK master slave FF, because of the gating on master latches S& R inputs, FF output change to1 even though K

and not J is asserted at the end of the Triggering pulse.This behaviour known as

(a) 0s latching

(b) Z latching

(c) 1’s latching

(d) don’t care latching

 

14. The sum of minimum values of tffpd and tcomb must be

(a) greater than thold

(b) less than Set up time margin

(c) greater than tsetup

(d) less than tclk

 

15. consider Bus holder circuit in 3.3V CMOS LVC. Specify a maximum over ride cutoff

(a) 100 mA

(b) 300micro A

(c) 200 micro A

(d) 500 μ A

 

16. GAL22V10 has tCF =

(a) 13 or 2.5

(b) 12 or 3.5

(c) 5 or 20

(d) 10 or 1.5

 

17. In serial to parallel conversion using parallel out shift register, the following ICs are used.

(a) threee 74 × 163, one 74 × 164, two 74 × 04, two74 × 27, one 74 × 377.

(b) two 74 ×163, one 74 × 164, two 74 × 04, one 74 × 27, one 74 × 377

(c) two 74 × 163, one 74 × 164, three 74 × 04, one 74 × 27, two74 × 377.

(d) two 74 × 163, four74 × 164, three 74 × 04, one 74 × 27, one 74 × 377.

 

18. MTBF (tr) is

(a) [erfc(tr/_)]/[T0.f.a2]

(b) [exp(tr)][T0.f ]

(c) [log(tr/_)]/[T1.f.a]

(d) [exp(tr/_)]/[T0.f.a]

 

19. EPROM (CMOS Technology) Write cycle is

(a) 50 - 100 μs /byte

(b) 70 - 500 μs /byte

(c) 100 - 500 μs /byte

(d) 10 - 50 μs/byte

 

20. In SRAMs output buffer is automatically disabled whenever is asserted ,even if OE L is asserted.

(a) WE H

(b) WE L

(c) CLR H

(d) CLR L