Thursday, April 24, 2008

A cellphone base station in every home



Sprints quotAiravequot femtocell is available in select US cities.

Sprint´s "Airave" femtocell is available in select US cities.


if you've ever had trouble getting a connection for your cellphone in your home, you could soon take matters into your own hands. Instead of relying on an overworked base station, consumers may be able to have their very own base stations inside their homes.

Called "femtocells," these miniature cellphone base stations are designed to be plugged into a home broadband or cable line. Then, they connect your call via the Internet to your service provider´s network, so you pay your Internet provider instead of your cellphone carrier. If you wander away from the short-range, low-power femtocell, your call will be handed over to the local base station, like normal.

The main advantage of a femtocell is, of course, improved coverage. A handful of femtocell companies already exist, and they claim that their technology offers much better clarity than Internet call systems such as VoIP that rely on Wi-Fi, where the signal is easily obstructed.

The new gadgets - femtocells are about the size of a cable box - could have other advantages, too. They could offer a cheap connection for downloading music, video, and podcasts to iPhones and their ilk. Femtocells could also prove valuable with the increasing popularity of 3G phones, whose high-frequency signals suffer from weakening over long distances. And, since femtocells could also have their own SIM cards, they could make calls themselves, such as alerting you when another cell phone enters your home.

However, femtocell makers still have a few challenges to face before the product is ready for market. Most important is the challenge of ensuring that cell phones in the home connect to the femtocell rather than the city´s base station (the "macrocell").

Security is another issue. If femtocells become a feature in every home, the devices will have to adjust their frequencies to avoid interference with neighboring lines.

Finally, the idea of installing a mini base station inside the home will likely concern some individuals, since it´s another source of microwaves. On the other hand, femtocells will allow cell phones to work at reduced power due to their proximity, so there´s a bit of a trade-off.

In February, the Mobile World Congress in Barcelona, Spain, found the technology promising, boosting the hopes of the companies that have invested heavily in femtocell research. For example, companies such as Ubiquisys and ip.access in the UK and Sprint in the US are betting that the advantages of the technology will overcome the challenges. While Sprint is already releasing heavily subsidized $50 femtocells in select US cities, other companies believe more testing is needed, and suggest a final price closer to $250.

Warner backs Sony Blu-ray format


Blu-ray stand at the Consumer Electronics Show in Las Vegas
Blu-ray's supporters have been celebrating Warner's decision
Warner Brothers is to release high definition films only in Sony's Blu-ray format, in a blow to rivals in the long-running format war.

Warner was the only major studio still releasing films both in the competing Blu-ray and HD DVD formats.

Five studios now back Blu-ray solely. Only Universal Pictures and Paramount Pictures favour HD DVD.

The backers of HD DVD deny their format is dead but admitted disappointment with the Warner decision.

Consumer choice

Walt Disney, Twentieth Century Fox, Metro-Goldwyn-Mayer and Sony Pictures are the other studios that only release in Blu-ray format.

Both formats deliver high definition pictures and sound and work with HD televisions, but they are not compatible with each other and neither will play on older DVD players.


Warner said it had opted for Blu-ray because 60% of its US high-definition sales last year had been in that format.

Warner Home Video will stop releasing new titles on HD DVD at the end of May.

The announcement forced a swift reaction from the HD DVD Promotional Group.

The organisation cancelled all the meetings it had scheduled with journalists at high profile Consumer Electronics Show (CES) in Las Vegas and called off a press conference booked for Sunday evening.

In a statement the HD DVD group said: ""While Warner's decision is a setback for HD DVD, the consumer has benefited from HD DVD's commitment to quality and affordability - a bar that is critical for the mainstream success of any format.

"We believe widespread adoption of a next generation format will ultimately be determined by the consumer," it added.

'A quick death'

Rich Greenfield at Pali Capital predicted that HD DVD would now "die a quick death" and predicted that would be good news for DVD sales.

HD DVD stand at CES, AP
Soonl only two studios will release movies in the HD DVD format
"While we still expect overall consumer spending on DVDs to decline at least 3% in 2008, the risk of an even worse 2008 DVD environment has most likely been avoided by Warner's early 2008 decision," he said.

Toshiba, a founding partner of the HD DVD standard, denied that its format was dead, with Akiyo Ozaka, president of Toshiba America Consumer Products saying that HD DVD "has not lost".

"We were very disappointed with Warner Brothers' announcement," he admitted at CES.

But he added: "Sales of HD DVD were very good last year, especially in October to December."

Wireless GPS systems

The new firmware code in the Jupiter 30 xLP and Jupiter 32 xLP improves time-to-first-fix in urban environments, significantly increases navigation sensitivity and provides greater stability

Navman Wireless OEM Solutions has incorporated the low-power SiRF technology into its GPS solutions. The Navman Wireless Jupiter 30 xLP and Jupiter 32 xLP extra low power modules feature the new 65nm SiRFstarIII GSC3e(f)/LPx chipset and offer up to 30% power savings over earlier modules. The Jupiter 30 xLP and Jupiter 32 xLP devices include the new SiRFstarIII GSW 3.2.5 firmware code and Navman software features including: Write-to-Flash for easy configuration storage and retrieval; Ephemeris Push for rapid satellite acquisitions and starts; and user-selectable profiles to maximise operation in a variety of environments.

The new firmware code improves time-to-first-fix in urban environments, significantly increases navigation sensitivity and provides greater stability, including improved response to transient conditions and improved jamming mitigation.

Tuesday, April 22, 2008

Remote Microscopy




A modular microscope attachment for cell phones could improve the quality of telemedi





Mobile microscopy: A cell phone incorporating a microscope (top) developed at the University of California, Berkeley, can capture and transmit pictures such as this 23x-magnification image of the freshwater crustacean Cyclops (bottom). Researchers hope that the device will allow patients in remote areas to send images of red blood cells and other diagnostic information to medical specialists.
Credit: David Breslauer

Researchers at the University of California, Berkeley, have developed a modular, high-magnification microscope attachment for cell phones. The device will enable health workers in remote, rural areas to take high-resolution images of a patient's blood cells using a cell-phone camera, and then transmit the photos to experts at medical centers.

The researchers hope that the innovation will help patients with blood disorders who live far from medical specialists get more accurately diagnosed and treated. "I wanted to make optical design relevant to today," says Daniel Fletcher, a professor of bioengineering at Berkeley. Fletcher's students found it relatively easy to integrate a simple arrangement of lenses with the cell-phone camera and transmit magnified images to a laptop using a Bluetooth attachment to the phone. The work prompted Fletcher to file a patent through the university and try to make a practical microscope. The researchers say that the cameras in late-model phones are capable of capturing all the details that a doctor would need to identify malaria parasites and cancer cells.

"The challenge was to make a low-cost, durable device with a long battery life," says David Breslauer, a graduate student in Fletcher's lab. "As engineers, we initially wanted to make a whiz-bang gadget to take pictures of both skin and blood. But people in the field told us, 'Once it gets too complicated, no one is going to want to use it. Make something simple that just does the task.'"

The total cost of the first prototype, built from off-the-shelf components, was $75. The current version provides its own sample illumination from cheap, low-power LEDs. The device comes in two versions: with a magnification of about 5 times, for taking images of moles and rashes, and with a magnification of about 60 times, for capturing the details of blood cells and parasites. The higher-magnification model--the larger of the two--is roughly the size and shape of a roll of quarters. Both scopes attach to the phone with a modified belt clip.

"Microscopy is still considered the gold standard" for malaria diagnosis, says Katherine Herz, a medical doctor and a fellow in health policy at Stanford University. "If microscopy could be done with portable equipment ... [it] might be adopted far more widely and prove extremely useful."

Fletcher plans to test the microscope cell phone in Uganda this summer. Initially, his lab will make prototypes, but eventually, it plans to hand off the design to a manufacturer. The Blum Center for Developing Economies at Berkeley, which provided initial funding, will help test the device in Kampala. The scheme is to train local personnel and provide them with the necessary equipment to take pictures of patients' blood on special slides, and then phone in the images to specialists who can identify and count malaria parasites.

The researchers also hope to collaborate with a telemedicine program at the University of California, Davis, that serves rural California. Leukemia patients in remote areas could use the microscope cell phone to transmit images for white blood cell counts.

Wireless ways for high-speed file swaps







New wireless personal networks promise ultra-fast data exchange over short distances
Illustration: NICTA



Gigabit wireless:
The Gi-Fi integrated wireless transceiver chip developed at the National ICT Research Centre, Australia. —


Move over Wi-Fi, Gi-Fi is here! They are not putting it quite that way, but recent developments hold out the hope that very large video and other files, can be swapped within seconds, by wireless devices operating over a few metres, in largely unused and unlicensed higher frequency bands. First tangible evidence

The first tangible evidence that Gi-Fi (the ‘Gi’ is for gigabit data rates) might be more than just a neat new acronym, came from Australia last week. Researchers at the Victoria Research Laboratory of National Information and Communication Technology Australia Ltd (NICTA), announced that they had developed the world’s first transmitter-receiver integrated on a single chip, operating at 60 GHz and fabricated using the complementary metal oxide semiconductor (CMOS) process. (http://nicta.com.au/news/current )

The chip, just 5 mm per side, has a tiny 1 mm antenna and uses the 60 GHz ‘millimetre-wave’ spectrum — an unlicensed band of 7 GHz between 57 GHZ and 64GHz. NICTA’s CEO David Skellern says the technology will allow the wireless transfer of audio and video files at rates up to 5 gigabits per second… almost ten times faster than what is currently possible. And the fabrication which uses a 130 nanometre CMOS process, may lead eventually to chips priced as low as $10.

There are a number of firsts here: One, developing high frequency radio components in a standard CMOS process rather than in silicon seems to be a major achievement. If the process can be scaled up, it holds out the possibility of low cost, low power chips which are also very high broadband.

To get a feel for the scale of achievement, consider the best we can achieve with today’s incumbent wireless technologies, Wi-Fi ,Wi-MAX or Bluetooth.

WiFi (WLAN, 802.11) operates in the 2.4 GHz band, has transfer rates of between 11 MBPS and 55 MBPS. WiMAX ( 802.16WiMAX) operates in the 2-11 GHz band and achieves data rates of up to 70 MBPS. Bluetooth (802.15Bluetooth) whose operational ranges are comparable to what can be achieved by the Australian Gi-Fi chip, is typically capable of 20 KBPS to 200 KBPS and in its fastest version, peaks at 55 MBPS. Second, this is one of the first practical applications in the band of what is being known as mw-WPAN, that is, millimeter wave Wireless Personal Area Network… or 802.15.3 to give it the correct designation. An IEEE Task Group no. 3C was formed in 2005 to develop this new WPAN alternative which promises to harness a relatively uncrowded, unlicensed band while offering the hope of data rates of at least 1 GBPS and typically 2 GBPS or better. (see entries for Task Group 3C at http://www.ieee802.org/15/ for technical details and future roadmap).

The potential of mw-WPAN for ultra fast data exchange has prompted companies like Intel, LG, Matsushita (Panasonic), NEC, Samsung, SiBEAM, Sony and Toshiba to form WirelessHD, an industry-led effort to define a specification for the next generation wireless digital network interface for consumer electronics products. Specifically, WirelessHD has a stated goal of enabling wireless connectivity for streaming high-definition content between source devices and high-definition displays. ( see http://www.wirelesshd.org ).

In fact the NICTA effort, says its Gigabit Wireless Project leader Prof Stan Skafidas, has been supported by key industry players like IBM, Synopsys, Cadence, Anritsu, Aglent, Microsoft and SUSS MicroTec, so clearly there is industry interest in exploiting any technology that might boost data rates and drop product costs, ten fold… an enticing possibility.

Usable prototypes

In an indoor environment, the NICTA Gi-Fi device ( usable prototypes may be less than a year away) is expected to work over a distance of up to 10 metres… which puts it somewhere between Bluetooth and WiFi, range-wise. What will it do for you and me? Consumers could typically download a high definition movie from a kiosk in a matter of seconds to a music player or smart phone and having got home, could play it on a home theatre system or store it on a home server for future viewing, again within a few seconds.

Maybe, it’s not that premature to say, “WiFi, it’s time to move over, the competition is here!”

Silent, microchip-sized 'fan' has no moving parts, yet produces enough wind to cool a laptop



Dan Schlitz of Thorrn Micro Technologies is one of the developers of a new solid-state micro-fan. Credit: Dan Schlitz and Vishal Singhal Thorrn Micro Technologies
Dan Schlitz of Thorrn Micro Technologies is one of the developers of a new, solid-state micro-fan. Credit: Dan Schlitz and Vishal Singhal, Thorrn Micro Technologies

Engineers harnessing the same physical property that drives silent household air purifiers have created a miniaturized device that is now ready for testing as a silent, ultra-thin, low-power and low maintenance cooling system for laptop computers and other electronic devices.

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The compact, solid-state fan, developed with support from NSF's Small Business Innovation Research program, is the most powerful and energy efficient fan of its size. It produces three times the flow rate of a typical small mechanical fan and is one-fourth the size.

Dan Schlitz and Vishal Singhal of Thorrn Micro Technologies, Inc., of Marietta, Ga. will present their RSD5 solid-state fan at the 24th Annual Semiconductor Thermal Measurement, Modeling and Management Symposium (Semi-Therm) in San Jose, Calif., on March 17, 2008. The device is the culmination of six years of research that began while the researchers were NSF-supported graduate students at Purdue University.

"The RSD5 is one of the most significant advancements in electronics cooling since heat pipes. It could change the cooling paradigm for mobile electronics," said Singhal.

The RSD5 incorporates a series of live wires that generate a micro-scale plasma (an ion-rich gas that has free electrons that conduct electricity). The wires lie within un-charged conducting plates that are contoured into half-cylindrical shape to partially envelop the wires.

Within the intense electric field that results, ions push neutral air molecules from the wire to the plate, generating a wind. The phenomenon is called corona wind.

"The technology is a breakthrough in the design and development of semiconductors as it brings an elegant and cost effective solution to the heating problems that have plagued the industry," said Juan Figueroa, the NSF SBIR program officer who oversaw the research.

With the breakthrough of the contoured surface, the researchers were able to control the micro-scale discharge to produce maximum airflow without risk of sparks or electrical arcing. As a result, the new device yields a breeze as swift as 2.4 meters per second, as compared to airflows of 0.7 to 1.7 meters per second from larger, mechanical fans.

The contoured platform is a part of the device heat sink, a trick that enabled Schlitz and Singhal to both eliminate some of the device's bulk and increase the effectiveness of the airflow.

"The technology has the power to cool a 25-watt chip with a device smaller than 1 cubic-cm and can someday be integrated into silicon to make self-cooling chips," said Schlitz.

This device is also more dust-tolerant than predecessors. While dust attraction is ideal for living-room-scale fans that that provide both air flow and filtration, debris can be a devastating obstacle when the goal is to cool an electrical component.

Monday, April 21, 2008

Using Microcontrollers


In How Electronic Gates Work, you learned about 7400-series TTL devices, as well as where to buy them and how to assemble them. What you found is that it can often take many gates to implement simple devices. For example, in the digital clock article, the clock we designed might contain 15 or 20 chips. One of the big advantages of a microcontroller is that software -- a small program you write and execute on the controller -- can take the place of many gates. In this article, therefore, we will use a microcontroller to create a digital clock. This is going to be a rather expensive digital clock (almost $200!), but in the process you will accumulate everything you need to play with microcontrollers for years to come. Even if you don't actually create this digital clock, you will learn a great deal by reading about it.

The microcontroller we will use here is a special-purpose device designed to make life as simple as possible. The device is called a "BASIC Stamp" and is created by a company called Parallax. A BASIC Stamp is a PIC microcontroller that has been customized to understand the BASIC programming language. The use of the BASIC language makes it extremely easy to create software for the controller. The microcontroller chip can be purchased on a small carrier board that accepts a 9-volt battery, and you can program it by plugging it into one of the ports on your desktop computer. It is unlikely that any manufacturer would use a BASIC Stamp in an actual production device -- Stamps are expensive and slow (relatively speaking). However, it is quite common to use Stamps for prototyping or for one-off demo products because they are so incredibly easy to set up and use.

They are called "Stamps," by the way, because they are about as big as a postage stamp.

Parallax makes two versions of the BASIC Stamp: the BS-1 and the BS-2. Here are some of the differences between the two models:

Spec BS-1BS-2
RAM14 bytes26 bytes
EEPROM256 bytes2 kilobytes
Max program lengthabout 75 instructionsabout 600 instructions
Execution speed2,000 lines/sec4,000 lines/sec
I/O pins816

The specific BASIC Stamp we will be using in this article is called the "BASIC Stamp Revision D" (pictured below).


The BASIC Stamp Revision D is a BS-1 mounted on carrier board with a 9-volt battery holder, a power regulator, a connection for a programming cable, header pins for the I/O lines and a small prototyping area. You could buy a BS-1 chip and wire the other components in on a breadboard. The Revision D simply makes life easier.

You can see from the previous table that you aren't going to be doing anything exotic with a BASIC stamp. The 75-line limit (the 256 bytes of EEPROM can hold a BASIC program about 75 lines long) for the BS-1 is fairly constraining. However, you can create some pretty neat stuff, and the fact that the Stamp is so small and battery operated means that it can go almost anywhere.

How Microcontrollers Work

Microcontrollers are hidden inside a surprising number of products these days. If your microwave oven has an LED or LCD screen and a keypad, it contains a microcontroller. All modern automobiles contain at least one microcontroller, and can have as many as six or seven: The engine is controlled by a microcontroller, as are the anti-lock brakes, the cruise control and so on. Any device that has a remote control almost certainly contains a microcontroller: TVs, VCRs and high-end stereo systems all fall into this category. Nice SLR and digital cameras, cell phones, camcorders, answering machines, laser printers, telephones (the ones with caller ID, 20-number memory, etc.), pagers, and feature-laden refrigerators, dishwashers, washers and dryers (the ones with displays and keypads)... You get the idea. Basically, any product or device that interacts with its user has a microcontroller buried inside.

In this article, we will look at microcontrollers so that you can understand what they are and how they work. Then we will go one step further and discuss how you can start working with microcontrollers yourself -- we will create a digital clock with a microcontroller! We will also build a digital thermometer. In the process, you will learn an awful lot about how microcontrollers are used in commercial products.

What is a Microcontroller?


A microcontroller is a computer. All computers -- whether we are talking about a personal desktop computer or a large mainframe computer or a microcontroller -- have several things in common:
  • All computers have a CPU (central processing unit) that executes programs. If you are sitting at a desktop computer right now reading this article, the CPU in that machine is executing a program that implements the Web browser that is displaying this page.
  • The CPU loads the program from somewhere. On your desktop machine, the browser program is loaded from the hard disk.
  • The computer has some RAM (random-access memory) where it can store "variables."
  • And the computer has some input and output devices so it can talk to people. On your desktop machine, the keyboard and mouse are input devices and the monitor and printer are output devices. A hard disk is an I/O device -- it handles both input and output.

The desktop computer you are using is a "general purpose computer" that can run any of thousands of programs. Microcontrollers are "special purpose computers." Microcontrollers do one thing well. There are a number of other common characteristics that define microcontrollers. If a computer matches a majority of these characteristics, then you can call it a "microcontroller":

  • Microcontrollers are "embedded" inside some other device (often a consumer product) so that they can control the features or actions of the product. Another name for a microcontroller, therefore, is "embedded controller."

  • Microcontrollers are dedicated to one task and run one specific program. The program is stored in ROM (read-only memory) and generally does not change.

  • Microcontrollers are often low-power devices. A desktop computer is almost always plugged into a wall socket and might consume 50 watts of electricity. A battery-operated microcontroller might consume 50 milliwatts.

  • A microcontroller has a dedicated input device and often (but not always) has a small LED or LCD display for output. A microcontroller also takes input from the device it is controlling and controls the device by sending signals to different components in the device.

    For example, the microcontroller inside a TV takes input from the remote control and displays output on the TV screen. The controller controls the channel selector, the speaker system and certain adjustments on the picture tube electronics such as tint and brightness. The engine controller in a car takes input from sensors such as the oxygen and knock sensors and controls things like fuel mix and spark plug timing. A microwave oven controller takes input from a keypad, displays output on an LCD display and controls a relay that turns the microwave generator on and off.

  • A microcontroller is often small and low cost. The components are chosen to minimize size and to be as inexpensive as possible.

  • A microcontroller is often, but not always, ruggedized in some way.

    The microcontroller controlling a car's engine, for example, has to work in temperature extremes that a normal computer generally cannot handle. A car's microcontroller in Alaska has to work fine in -30 degree F (-34 C) weather, while the same microcontroller in Nevada might be operating at 120 degrees F (49 C). When you add the heat naturally generated by the engine, the temperature can go as high as 150 or 180 degrees F (65-80 C) in the engine compartment.

    On the other hand, a microcontroller embedded inside a VCR hasn't been ruggedized at all.

The actual processor used to implement a microcontroller can vary widely. For example, the cell phone shown on Inside a Digital Cell Phone contains a Z-80 processor. The Z-80 is an 8-bit microprocessor developed in the 1970s and originally used in home computers of the time. The Garmin GPS shown in How GPS Receivers Work contains a low-power version of the Intel 80386, I am told. The 80386 was originally used in desktop computers.

In many products, such as microwave ovens, the demand on the CPU is fairly low and price is an important consideration. In these cases, manufacturers turn to dedicated microcontroller chips -- chips that were originally designed to be low-cost, small, low-power, embedded CPUs. The Motorola 6811 and Intel 8051 are both good examples of such chips. There is also a line of popular controllers called "PIC microcontrollers" created by a company called Microchip. By today's standards, these CPUs are incredibly minimalistic; but they are extremely inexpensive when purchased in large quantities and can often meet the needs of a device's designer with just one chip.

A typical low-end microcontroller chip might have 1,000 bytes of ROM and 20 bytes of RAM on the chip, along with eight I/0 pins. In large quantities, the cost of these chips can sometimes be just pennies. You certainly are never going to run Microsoft Word on such a chip -- Microsoft Word requires perhaps 30 megabytes of RAM and a processor that can run millions of instructions per second. But then, you don't need Microsoft Word to control a microwave oven, either. With a microcontroller, you have one specific task you are trying to accomplish, and low-cost, low-power performance is what is important.

Thursday, April 17, 2008

List of Intel microprocessors


The 4-bit processors

Intel 4004: first single-chip microprocessor

MCS-4 Family:

  • 4004-CPU
  • 4001-ROM & 4 Bit Port
  • 4002-RAM & 4 Bit Port
  • 4003-10 Bit Shift Registr
  • 4008-Memory+I/O Interface
  • 4009-Memory+I/O Interface

[edit] 4040

  • Introduced 4th Qtr, 1974 ADAM
  • Clock speed of 500 kHz to 740 kHz using 4 to 5.185 MHz crystals
  • 0.06 MIPS
  • Bus Width 4 bits (multiplexed address/data due to limited pins)
  • PMOS
  • Number of Transistors 3,000 at 10 µm
  • Addressable Memory 640 bytes
  • Program Memory 8 KB
  • Interrupts
  • Enhanced version of 4004

MCS-40 Family:

  • 4040-CPU
  • 4101-1024-bit (256 x 4) Static RAM w/Separate I/O
  • 4201-4 MHz Clock Generator
  • 4207/4209/4211-General Purpose Byte I/O Port
  • 4265-Programmable General Purpose I/O Device
  • 4269-Programmable Keyboard Display Device
  • 4289-Standard Memory Interface for MCS-4/40
  • 4308-8192-bit (1024 x 8) ROM w/ 4-bit I/O Ports
  • 4316-16384-bit (2048 x 8) Static ROM
  • 4702-2048-bit (256 x 8) EPROM
  • 4801-5.185 MHz Clock Generator Crystal for 4004/4201A or 4040/4201A

[edit] The 8-bit processors

[edit] 8008

  • Introduced April 1, 1972
  • Clock speed 500 kHz (8008-1: 800 kHz)
  • 0.05 MIPS
  • Bus Width 8 bits (multiplexed address/data due to limited pins)
  • PMOS
  • Number of Transistors 3,500 at 10 µm
  • Addressable memory 16 KB
  • Typical in dumb terminals, general calculators, bottling machines
  • Developed in tandem with 4004
  • Originally intended for use in the Datapoint 2200 terminal

[edit] 8080

[edit] 8085

  • Introduced March 1976
  • Clock speed 5 MHz
  • 0.37 MIPS
  • Bus Width 8 bits data, 16 bits address
  • Number of Transistors 6,500 at 3 µm
  • Assembly language downwards compatible with 8080.
  • Used in Toledo scale. Also was used as a computer peripheral controller - modems, harddisks, etc...
  • CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable.
  • High level of integration, operating for the first time on a single 5 volt power supply, from 12 volts previously. Also featured two serial I/O connection,3 maskable interrupts,1 Non-maskable,1 programmable,status,DMA.

MCS-85 Family:

  • 8085-CPU
  • 8155-RAM+ 3 I/O Ports+Timer
  • 8156-RAM+ 3 I/O Ports+Timer
  • 8185-SRAM
  • 8202-Dynamic RAM Controller
  • 8203-Dynamic RAM Controller
  • 8205-1 Of 8 Binary Decoder
  • 8206-Error Detection & Correction Unit
  • 8207-DRAM Controller
  • 8210-TTL To MOS Shifter & High Voltage Clock Driver
  • 8212-8 Bit I/O Port
  • 8216-4 Bit Parallel Bidirectional Bus Driver
  • 8218/8219-Bus Controller
  • 8222-Dynamic RAM Refresh Controller
  • 8226-4 Bit Parallel Bidirectional Bus Driver
  • 8231-Arithmetic Processing Unit
  • 8232-Floating Point Processor
  • 8237-DMA Controller
  • 8251-Communication Controller
  • 8253-Programmable Interval Timer
  • 8254-Programmable Interval Timer
  • 8255-Programmable Peripheral Interface
  • 8256-Multifunction Support Controller
  • 8257-DMA Controller
  • 8259-Programmable Interrupt Controller
  • 8271-Programmable Floppy Disk Controller
  • 8272-Single/Double Density Floppy Disk Controller
  • 8273-Programmable HDLC/SDLC Protocol Controller
  • 8274-Multi-Protocol Serial Controller
  • 8275-CRT Controller
  • 8276-Small System CRT Controller
  • 8278-Programmable KeyBoard Interface
  • 8279-KeyBoard/Display Controller
  • 8282-8-bit Non-Inverting Latch with Output Buffer
  • 8283-8-bit Inverting Latch with Output Buffer
  • 8291-GPIB Talker/Listener
  • 8292-GPIB Controller
  • 8293-GPIB Transceiver
  • 8294-Data Encryption/Decryption Unit+1 O/P Port
  • 8295-Dot Matrix Printer Controller
  • 8296-GPIB Transceiver
  • 8297-GPIB Transceiver
  • 8355-16,384-bit (2048 x 8) ROM with I/O
  • 8604-4096-bit (512 x 8) PROM
  • 8702-2K-bit (256 x 8 ) PROM
  • 8755-EPROM+2 I/O Ports

[edit] The bit-slice processor

[edit] 3000 Family

Introduced 3rd Qtr, 1974 Members of the family

  • 3001-Microcontrol Unit
  • 3002-2-bit Arithmetic Logic Unit slice
  • 3003-Look-ahead Carry Generator
  • 3205-High-Speed 6-bit Latch
  • 3207-Quad Bipolar-to-MOS Level Shifter and Driver
  • 3208-Hex Sense Amp and Latch for MOS Memories
  • 3210-TTL-to-MOS Level Shifter and High Voltage Clock Driver
  • 3211-ECL-to-MOS Level Shifter and High Voltage Clock Driver
  • 3212-Multimode Latch Buffer
  • 3214-Interrupt Control Unit
  • 3216/3226-Parallel,Inverting Bi-Directional Bus Driver
  • 3222-Refresh Controller for 4K NMOS DRAMs
  • 3232-Address Multiplexer and Refresh Counter for 4K DRAMs
  • 3235-Quad Bipolar-to-MOS Driver
  • 3242-Address Multiplexer and Refresh Counter for 16K DRAMs
  • 3245-Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K
  • 3246-Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K
  • 3404-High-Speed 6-bit Latch
  • 3408-Hex Sense Amp and Latch for MOS Memories

Bus Width 2-n bits data/address (depending on number of slices used)

[edit] Signal Processor

[edit] 2900 Family

  • 2910-PCM CODEC – µ LAW
  • 2911-PCM CODEC – A LAW
  • 2912-PCM Line Filters
  • 2920-Signal Processor

[edit] Digital Clocks Processor

[edit] 5000 Family

These devices are CMOS technology.

  • 5101-1024-bit (256 x 4) Static RAM
  • 5201/5202-LCD Decoder-Driver
  • 5204-Time Seconds/Date LCD Decoder-Driver
  • 5234-Quad CMOS-to-MOS Level Shifter and Driver for 4K NMOS RAMs
  • 5235-Quad CMOS TTL-to-MOS Level Shifter and Driver for 4K NMOS
  • 5244-Quad CCD Clock Driver
  • 5801-Low Power Oscillator-Divider
  • 5810-Single Chip LCD Time/Seconds/Date Watch Circuit

[edit] The 16-bit processors: origin of x86

[edit] 8086

  • Introduced June 8, 1978
  • Clock speeds:
    • 5 MHz with 0.33 MIPS
    • 8 MHz with 0.66 MIPS
    • 10 MHz with 0.75 MIPS
  • The memory is divided into odd and even banks. It accesses both the banks simultaneuosly in order to read 16 bit of data in one clock cycle.
  • Bus Width 16 bits data, 20 bits address
  • Number of Transistors 29,000 at 3 µm
  • Addressable memory 1 megabyte
  • 10X the performance of 8080
  • Used in portable computing
  • Used segment registers to access more than 64 KB of data at once, bane of programmers' existence for years to come

[edit] 8088

  • Introduced June 1, 1979
  • Clock speeds:
    • 4.77 MHz with 0.33 MIPS
    • 9 MHz with 0.75 MIPS
  • Internal architecture 16 bits
  • External bus Width 8 bits data, 20 bits address
  • Number of Transistors 29,000 at 3 µm
  • Addressable memory 1 megabyte
  • Identical to 8086 except for its 8 bit external bus (hence an 8 instead of a 6 at the end)
  • Used in IBM PCs and PC clones


iAPX 432 (chronological entry)

[edit] 80186

  • Introduced 1982
  • Used mostly in embedded applications - controllers, point-of-sale systems, terminals, and the like
  • Used in several MS-DOS non-PC-Compatible computers including RM Nimbus, Tandy 2000
  • Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor
  • Later renamed the iAPX 186

[edit] 80188

  • A version of the 80186 with an 8-bit external data bus
  • Later renamed the iAPX 188

[edit] 80286

  • Introduced February 1, 1982
  • Clock speeds:
    • 6 MHz with 0.9 MIPS
    • 8 MHz, 10 MHz with 1.5 MIPS
    • 12.5 MHz with 2.66 MIPS
    • 16 MHz, 20 MHz and 25 MHz available.
  • Bus Width 16 bits
  • Included memory protection hardware to support multitasking operating systems with per-process address space
  • Number of Transistors 134,000 at 1.5 µm
  • Addressable memory 16 MB (16 MiB)
  • Added protected-mode features to 8086 with essentially the same instruction set
  • 3-6X the performance of the 8086
  • Widely used in IBM-PC AT and AT clones at the time

32-bit processors: the non-x86 microprocessors

[edit] iAPX 432

  • Introduced January 1, 1981 as Intel's first 32-bit microprocessor
  • Object/capability architecture
  • Microcoded operating system primitives
  • One terabyte virtual address space
  • Hardware support for fault tolerance
  • Two-chip General Data Processor (GDP), consists of 43201 and 43202
  • 43203 Interface Processor (IP) interfaces to I/O subsystem
  • 43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
  • 43205 Memory Control Unit (MCU)
  • Architecture and execution unit internal data paths 32 bit
  • Clock speeds:
    • 5 MHz
    • 7 MHz
    • 8 MHz

i960 aka 80960

  • Introduced April 5, 1988
  • RISC-like 32-bit architecture
  • Predominantly used in embedded systems
  • Evolved from the capability processor developed for the BiiN joint venture with Siemens
  • Many variants identified by two-letter suffixes.


80386SX (chronological entry)


80376 (chronological entry)

[edit] XScale

  • Introduced August 23, 2000
  • 32-bit RISC microprocessor based on the ARM architecture
  • Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors.

32-bit processors: the 80386 range

80386DX

  • Introduced October 17, 1985
  • Clock speeds:
    • 16 MHz with 5 to 6 MIPS
    • 20 MHz with 6 to 7 MIPS, introduced 16 February 1987
    • 25 MHz with 8.5 MIPS, introduced 4 April 1988
    • 33 MHz with 11.4 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced 10 April 1989
  • Bus Width 32 bits
  • Number of Transistors 275,000 at 1 µm
  • Addressable memory 4 GB (4 GiB)
  • Virtual memory 64 TB (64 TiB)
  • First x86 chip to handle 32-bit data sets
  • Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required by Windows 95 and OS/2 Warp
  • Used in Desktop computing
  • Can address enough memory to manage an eight-page history of every person on Earth


80960 (i960) (chronological entry)

80386SX

  • Introduced June 16, 1988
  • Clock speeds:
  • Internal architecture 32 bits
  • External data bus width 16 bits
  • External address bus width 24 bits
  • Number of Transistors 275,000 at 1 µm
  • Addressable memory 16 MB
  • Virtual memory 32 GB
  • Narrower buses enable low-cost 32-bit processing
  • Used in entry-level desktop and portable computing
  • No Math Co-Processor

[edit] 80376

  • Introduced January 16, 1989; Discontinued June 15, 2001
  • Variant of 386 intended for embedded systems
  • No "real mode", starts up directly in "protected mode"
  • Replaced by much more successful 80386EX from 1994


80860 (i860) (chronological entry)


80486DX (chronological entry)

[edit] 80386SL

  • Introduced October 15, 1990
  • Clock speeds:
  • Internal architecture 32 bits
  • External bus width 16 bits
  • Number of Transistors 855,000 at 1 µm
  • Addressable memory 4 GB
  • Virtual memory 1 TB
  • First chip specifically made for portable computers because of low power consumption of chip
  • Highly integrated, includes cache, bus, and memory controllers


80486SX/DX2/SL, Pentium, 80486DX4 (chronological entries)

[edit] 80386EX

  • Introduced August 1994
  • Variant of 80386SX intended for embedded systems
  • Static core, i.e. may run as slowly (and thus, power efficiently) as desired, down to full halt
  • On-chip peripherals:
    • Clock and power mgmt
    • Timers/counters
    • Watchdog timer
    • Serial I/O units (sync and async) and parallel I/O
    • DMA
    • RAM refresh
    • JTAG test logic
  • Significantly more successful than the 80376
  • Used aboard several orbiting satellites and microsatellites
  • Used in NASA's FlightLinux project

32-bit processors: the 80486 range

[edit] 80486DX

  • Introduced April 10, 1989
  • Clock speeds:
    • 25 MHz with 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
    • 33 MHz with 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KB L2), introduced 7 May 1990
    • 50 MHz with 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KB L2), introduced 24 June 1991
  • Bus Width 32 bits
  • Number of Transistors 1.2 million at 1 µm; the 50 MHz was at 0.8 µm
  • Addressable memory 4 GB
  • Virtual memory 1 TB
  • Level 1 cache of 8 KB on chip
  • Math coprocessor on chip
  • 50X performance of the 8088
  • Used in Desktop computing and servers
  • Family 4 model 3


80386SL (chronological entry)

[edit] 80486SX

  • Introduced April 22, 1991
  • Clock speeds:
  • Bus Width 32 bits
  • Number of Transistors 1.185 million at 1 µm and 900,000 at 0.8 µm
  • Addressable memory 4 GB
  • Virtual memory 1 TB
  • Identical in design to 486DX but without math coprocessor. The first version was an 80486DX with disabled mathco in the chip and different pin configuration. If the user needed math co capabilities, he must add 487SX which was actually an 486DX with different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPU's with only 1 turned on)
  • Used in low-cost entry to 486 CPU desktop computing
  • Upgradable with the Intel OverDrive processor
  • Family 4 model 2

[edit] 80486DX2

  • Introduced March 3, 1992
  • Clock speeds:
    • 20 MHz
    • 40 MHz
    • 50 MHz
    • 66 MHz
    • 100 MHz

[edit] 80486SL

  • Introduced November 9, 1992
  • Clock speeds:
    • 20 MHz with 15.4MIPS
    • 25 MHz with 19 MIPS
    • 33 MHz with 25 MIPS
  • Bus Width 32 bits
  • Number of Transistors 1.4 million at 0.8 µm
  • Addressable memory 4 GB
  • Virtual memory 1 TB
  • Used in notebook computers
  • Family 4 model 3


Pentium (chronological entry)

[edit] 80486DX4

  • Introduced March 7, 1994
  • Clock speeds:
    • 75 MHz with 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KB L2)
    • 100 MHz with 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KB L2)
  • Number of Transistors 1.6 million at 0.6 µm
  • Bus width 32 bits
  • Addressable memory 4 GB
  • Virtual memory 64 TB
  • Pin count 168 PGA Package, 208 sq ftP Package
  • Die size 345 mm²
  • Used in high performance entry-level desktops and value notebooks
  • Family 4 model 8

[edit] 32-bit processors: the Pentium ("I")

[edit] Pentium ("Classic")

  • Bus width 64 bits
  • System bus speed 60 or 66 MHz
  • Address bus 32 bits
  • Addressable Memory 4 GB
  • Virtual Memory 64 MB
  • Superscalar architecture brought 5X the performance of the 33 MHz 486DX processor
  • Runs on 5 volts
  • Used in desktops
  • 16 KB of L1 cache
  • P5 - 0.8 µm process technology
    • Introduced March 22, 1993
    • Number of transistors 3.1 million
    • Socket 4 273 pin PGA processor package
    • Package dimensions 2.16" x 2.16"
    • Family 5 model 1
    • Variants
      • 60 MHz with 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256 KB L2)
      • 66 MHz with 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256 KB L2)
  • P54 - 0.6 µm process technology
  • P54C - 0.35 µm process technology
    • Number of transistors 3.3 million
    • 90 mm² die size
    • Family 5 model 2
    • Variants


80486DX4 (chronological entry)


80386EX (Intel386 EX) (chronological entry)


Pentium Pro (chronological entry)

[edit] Pentium with MMX Technology

[edit] 32-bit processors: P6/Pentium M microarchitecture

[edit] Pentium Pro

  • Introduced November 1, 1995
  • Precursor to Pentium II and III
  • Primarily used in server systems
  • Socket 8 processor package (387 pins) (Dual SPGA)
  • Number of transistors 5.5 million
  • Family 6 model 1
  • 0.6 µm process technology
    • 16 KB L1 cache
    • 256 KB integrated L2 cache
    • 60 MHz system bus speed
    • Variants
      • 150 MHz
  • 0.35 µm process technology, or 0.35 µm CPU with 0.6 µm L2 cache
    • Number of transistors 5.5 million
    • 512 KB or 256 KB integrated L2 cache
    • 60 or 66 MHz system bus speed
    • Variants
      • 166 MHz (66 MHz bus speed, 512 KB 0.35 µm cache) Introduced November 1, 1995
      • 180 MHz (60 MHz bus speed, 256 KB 0.6 µm cache) Introduced November 1, 1995
      • 200 MHz (66 MHz bus speed, 256 KB 0.6 µm cache) Introduced November 1, 1995
      • 200 MHz (66 MHz bus speed, 512 KB 0.35 µm cache) Introduced November 1, 1995
      • 200 MHz (66 MHz bus speed, 1 MB 0.35 µm cache) Introduced August 18, 1997

[edit] Pentium II

[edit] Celeron (Pentium II-based)


Pentium II Xeon (chronological entry)

[edit] Pentium III

[edit] Pentium II and III Xeon

  • PII Xeon
  • PIII Xeon
    • Introduced October 25, 1999
    • Number of transistors: 9.5 million at 0.25 µm or 28 million at 0.18 µm)
    • L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated)
    • Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
    • System Bus Speed 133 MHz (256 KB L2 cache) or 100 MHz (1 - 2 MB L2 cache)
    • System Bus Width 64 bit
    • Addressable memory 64 GB
    • Used in two-way servers and workstations (256 KB L2) or 4- and 8-way servers (1 - 2 MB L2)
    • Family 6 model 10
    • Variants

[edit] Celeron (Pentium III Coppermine-based)


XScale (chronological entry)


Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 (chronological entries)

  • Introduced April 2000 – July 2002
  • See main entries

[edit] Celeron (Pentium III Tualatin-based)

  • Tualatin Celeron - 0.13 µm process technology
    • 32 KB L1 cache
    • 256 KB Advanced Transfer L2 cache
    • 100 MHz system bus speed
    • Socket 370
    • Family 6 model 11
    • Variants
      • 1.0 GHz
      • 1.1 GHz
      • 1.2 GHz
      • 1.3 GHz
      • 1.4 GHz

[edit] Pentium M

  • Banias 0.13 µm process technology
    • Introduced March 2003
    • 64 KB L1 cache
    • 1 MB L2 cache (integrated)
    • Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline
    • Number of transistors 77 million
    • Micro-FCPGA, Micro-FCBGA processor package
    • Heart of the Intel mobile "Centrino" system
    • 400 MHz Netburst-style system bus
    • Family 6 model 9
    • Variants
      • 900 MHz (Ultra low voltage)
      • 1.0 GHz (Ultra low voltage)
      • 1.1 GHz (Low voltage)
      • 1.2 GHz (Low voltage)
      • 1.3 GHz
      • 1.4 GHz
      • 1.5 GHz
      • 1.6 GHz
      • 1.7 GHz
  • Dothan 0.09 µm (90 nm) process technology
    • Introduced May 2004
    • 2 MB L2 cache
    • Revised data prefetch unit
    • 400 MHz Netburst-style system bus
    • 21W TDP
    • Variants
      • 1.00 GHz (Pentium M 723) (Ultra low voltage, 5W TDP)
      • 1.10 GHz (Pentium M 733) (Ultra low voltage, 5W TDP)
      • 1.20 GHz (Pentium M 753) (Ultra low voltage, 5W TDP)
      • 1.30 GHz (Pentium M 718) (Low voltage, 10W TDP)
      • 1.40 GHz (Pentium M 738) (Low voltage, 10W TDP)
      • 1.50 GHz (Pentium M 758) (Low voltage, 10W TDP)
      • 1.60 GHz (Pentium M 778) (Low voltage, 10W TDP)
      • 1.40 GHz (Pentium M 710)
      • 1.50 GHz (Pentium M 715)
      • 1.60 GHz (Pentium M 725)
      • 1.70 GHz (Pentium M 735)
      • 1.80 GHz (Pentium M 745)
      • 2.00 GHz (Pentium M 755)
      • 2.10 GHz (Pentium M 765)
  • Dothan 533 0.09 µm (90 nm) process technology
    • Introduced Q1 2005
    • Same as Dothan except with a 533 MHz NetBurst-style system bus and 27W TDP
    • Variants
      • 1.60 GHz (Pentium M 730)
      • 1.73 GHz (Pentium M 740)
      • 1.86 GHz (Pentium M 750)
      • 2.00 GHz (Pentium M 760)
      • 2.13 GHz (Pentium M 770)
      • 2.26 GHz (Pentium M 780)
  • Stealey 0.09 µm (90 nm) process technology
    • Introduced Q2 2007
    • 512 KB L2, 3W TDP
    • Variants
      • 600 MHz (A100)
      • 800 MHz (A110)

[edit] Celeron M

  • Banias-512 0.13 µm process technology
    • Introduced March 2003
    • 64 KB L1 cache
    • 512 KB L2 cache (integrated)
    • SSE2 SIMD instructions
    • No SpeedStep technology, is not part of the 'Centrino' package
    • Family 6 model 9
    • Variants
      • 310 - 1.20 GHz
      • 320 - 1.30 GHz
      • 330 - 1.40 GHz
      • 340 - 1.50 GHz
  • Dothan-1024 90 nm process technology
    • 64 KB L1 cache
    • 1 MB L2 cache (integrated)
    • SSE2 SIMD instructions
    • No SpeedStep technology, is not part of the 'Centrino' package
    • Variants
      • 350 - 1.30 GHz
      • 350J - 1.30 GHz, with Execute Disable bit
      • 360 - 1.40 GHz
      • 360J - 1.40 GHz, with Execute Disable bit
      • 370 - 1.50 GHz, with Execute Disable bit
        • Family 6, Model 13, Stepping 8[2]
      • 380 - 1.60 GHz, with Execute Disable bit
      • 390 - 1.70 GHz, with Execute Disable bit
  • Yonah-1024 65 nm process technology
    • 64 KB L1 cache
    • 1 MB L2 cache (integrated)
    • SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit
    • No SpeedStep technology, is not part of the 'Centrino' package
    • Variants
      • 410 - 1.46 GHz
      • 420 - 1.60 GHz,
      • 423 - 1.06 GHz (ultra low voltage)
      • 430 - 1.73 GHz
      • 440 - 1.86 GHz
      • 443 - 1.20 GHz (ultra low voltage)
      • 450 - 2.00 GHz
  • Merom-1024 65 nm process technology
    • 64 KB L1 cache
    • 1 MB L2 cache (integrated)
    • SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit, 64-bit
    • No SpeedStep technology, is not part of the 'Centrino' package
    • Variants
      • 520 - 1.60 GHz
      • 530 - 1.73 GHz
      • 540 - 1.86 GHz
      • 550 - 2.00 GHz

[edit] Intel Core

  • Yonah 0.065 µm (65 nm) process technology
    • Introduced January 2006
    • 667 MHz frontside bus
    • 2 MB (Shared on Duo) L2 cache
    • SSE3 SIMD instructions
    • 31W TDP (T**** versions)
    • Variants:
      • Intel Core Duo T2700 2.33 GHz
      • Intel Core Duo T2600 2.16 GHz
      • Intel Core Duo T2500 2.00 GHz
      • Intel Core Duo T2400 1.83 GHz
      • Intel Core Duo T2300 1.66 GHz
      • Intel Core Duo T2050 1.60 GHz
      • Intel Core Duo L2500 1.83 GHz (Low voltage, 15W TDP)
      • Intel Core Duo L2400 1.66 GHz (Low voltage, 15W TDP)
      • Intel Core Duo L2300 1.50 GHz (Low voltage, 15W TDP)
      • Intel Core Duo U2500 1.20 GHz (Ultra low voltage, 9W TDP)
      • Intel Core Solo T1350 1.86 GHz (533 FSB)
      • Intel Core Solo T1300 1.66 GHz
      • Intel Core Solo T1200 1.50 GHz [3]

[edit] Dual-Core Xeon LV

  • Sossaman 0.065 µm (65 nm) process technology
    • Introduced March 2006
    • Based on Yonah core, with SSE3 SIMD instructions
    • 667 MHz frontside bus
    • 2 MB Shared L2 cache
    • Variants
      • 2.0 GHz

[edit] Intel Pentium Dual-Core

  • 0.065 µm (65 nm) process technology
    • 533 MHz frontside bus
    • 1 MB Shared L2 cache
    • SSE3 SIMD instructions
    • Variants:
      • Pentium dual-core T2080 1.73 GHz
      • Pentium dual-core T2060 1.60 GHz

[edit] 32-bit processors: NetBurst microarchitecture

[edit] Pentium 4

  • 0.18 µm process technology (1.40 and 1.50 GHz)
    • Introduced November 20, 2000
    • L2 cache was 256 KB Advanced Transfer Cache (Integrated)
    • Processor Package Style was PGA423, PGA478
    • System Bus Speed 400 MHz
    • SSE2 SIMD Extensions
    • Number of Transistors 42 million
    • Used in desktops and entry-level workstations
  • 0.18 µm process technology (1.7 GHz)
    • Introduced April 23, 2001
    • See the 1.4 and 1.5 chips for details
  • 0.18 µm process technology (1.6 and 1.8 GHz)
    • Introduced July 2, 2001
    • See 1.4 and 1.5 chips for details
    • Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in Battery Optimized Mode
    • Power <1>
    • Used in full-size and then light mobile PCs
  • 0.18 µm process technology Willamette (1.9 and 2.0 GHz)
  • Family 15 model 1
  • Pentium 4 (2 GHz, 2.20 GHz)
  • Pentium 4 (2.4 GHz)
  • 0.13 µm process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6, 2.8(OEM),3.0(OEM) GHz)
    • Improved branch prediction and other microcodes tweaks
    • 512 KB integrated L2 cache
    • Number of transistors 55 million
    • 400 MHz system bus.
  • Family 15 model 2
  • 0.13 µm process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)
  • 0.13 µm process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)
    • 800 MHz system bus (all versions include Hyper Threading)
    • 6500 to 10000 MIPS


Itanium (chronological entry)

[edit] Xeon

  • Official designation now Xeon, i.e. not "Pentium 4 Xeon"
  • Xeon 1.4, 1.5, 1.7 GHz
    • Introduced May 21, 2001
    • L2 cache was 256 KB Advanced Transfer Cache (Integrated)
    • Processor Package Style was Organic Lan Grid Array 603 (OLGA 603)
    • System Bus Speed 400 MHz
    • SSE2 SIMD Extensions
    • Used in high-performance and mid-range dual processor enabled workstations
  • Xeon 2.0 GHz and up to 3.6 GHz


Itanium 2 (chronological entry)

[edit] Mobile Pentium 4-M

  • 0.13 µm process technology
  • 55 million transistors
  • cache L2 512 KB
  • BUS a 400 MHz
  • Supports up to 1 GB of DDR 266 MHz Memory
  • Supports ACPI 2.0 and APM 1.2 System Power Management
  • 1.3 V - 1.2 V (SpeedStep)
  • Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W
  • Sleep Power 5 W (1.2 V)
  • Deeper Sleep Power = 2.9 W (1.0 V)
    • 1.40 GHz - 23 April 2002
    • 1.50 GHz - 23 April 2002
    • 1.60 GHz - 4 March 2002
    • 1.70 GHz - 4 March 2002
    • 1.80 GHz - 23 April 2002
    • 1.90 GHz - 24 June 2002
    • 2.00 GHz - 24 June 2002
    • 2.20 GHz - 16 September 2002
    • 2.40 GHz - 14 January 2003
    • 2.40 GHz - 14 January 2003
    • 2.50 GHz - 16 April 2003
    • 2.60 GHz - 11 June 2003

[edit] Pentium 4 EE

  • Introduced September 2003
  • EE = "Extreme Edition"
  • Built from the Xeon's "Gallatin" core, but with 2 MB cache

[edit] Pentium 4E

  • Introduced February 2004
  • built on 0.09 µm (90 nm) process technology Prescott (2.4A, 2.8, 2.8A, 3.0, 3.2, 3.4, 3.6, 3.8) 1 MB L2 cache
  • 533 MHz system bus (2.4A and 2.8A only)
  • Number of Transistors 125 million on 1 MB Models
  • Number of Transistors 169 million on 2 MB Models
  • 800 MHz system bus (all other models)
  • Hyper-Threading support is only available on CPUs using the 800 MHz system bus.
  • The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater clock speeds.
  • 7500 to 11000 MIPS
  • LGA-775 versions are in the 5xx series (32-bit) and 5x1 series (with Intel 64)
  • The 6xx series has 2 MB L2 cache and Intel 64

[edit] Pentium 4F

  • Introduced Spring 2004
  • same core as 4E, "Prescott"
  • 3.2–3.6 GHz
  • starting with the D0 stepping of this processor, Intel 64 64-bit extensions has also been incorporated

[edit] 64-bit processors: IA-64

  • New instruction set, not at all related to x86.
  • Before the feature was eliminated (Montecito, July 2006) IA-64 processors supported 32-bit x86 in hardware, but slowly.

[edit] Itanium

[edit] Itanium 2

  • Released July 2002
  • 900 MHz - 1.6 GHz


Pentium M (chronological entry)


Pentium 4EE, 4E (chronological entries)

  • Introduced September 2003, February 2004, respectively
  • See main entries

[edit] 64-bit processors: Intel64 - NetBurst

  • Intel® Extended Memory 64 Technology
  • Mostly compatible with AMD's AMD64 architecture
  • Introduced Spring 2004, with the Pentium 4F (D0 and later P4 steppings)

[edit] Pentium 4F

  • Prescott-2M built on 0.09 µm (90 nm) process technology
  • 2.8-3.8 GHz (model numbers 6x0)
  • Introduced February 20, 2005
  • Same features as Prescott with the addition of:-
    • 2 MB cache
    • Intel 64bit
    • Enhanced Intel SpeedStep Technology (EIST)
  • Cedar Mill built on 0.065 µm (65 nm) process technology
  • 3.0-3.6 (model numbers 6x1)
  • Introduced January 16, 2006
  • die shrink of Prescott-2M
  • Same features as Prescott-2M

[edit] Pentium D

  • Smithfield - 90 nm process technology (2.66–3.2 GHz)
    • Introduced May 26, 2005
    • 2.66–3.2 GHz (model numbers 805-840)
    • Number of Transistors 230 million
    • 1 MB x 2 (non-shared, 2 MB total) L2 cache
    • Cache coherency between cores requires communication over the FSB
    • Performance increase of 60% over similarly clocked Prescott
    • 2.66 GHz (533 MHz FSB) Pentium D 805 introduced December 2005
    • Contains 2x Prescott dies in one package
  • Presler - 65 nm process technology (2.8–3.6 GHz)
    • Introduced January 16, 2006
    • 2.8–3.6 GHz (model numbers 915-960)
    • Number of Transistors 376 million
    • 2 MB x 2 (non-shared, 4 MB total) L2 cache
    • Contains 2x Cedar Mill dies in one package

[edit] Pentium Extreme Edition

  • Smithfield - 90 nm process technology (3.2 GHz)
    • Variants
      • Pentium 840 EE - 3.20 GHz (2 x 1 MB L2)
  • Presler - 65 nm process technology (3.46, 3.73)
    • 2 MB x 2 (non-shared, 4 MB total) L2 cache
    • Variants
      • Pentium 955 EE - 3.46 GHz
      • Pentium 965 EE - 3.73 GHz

[edit] Xeon

  • Nocona
  • Irwindale
  • Cranford
    • Introduced April 2005
    • MP version of Nocona
  • Potomac
    • Introduced April 2005
    • Cranford with 8 MB of L3 cache
  • Paxville DP (2.8 GHz)
    • Introduced October 10, 2005
    • Dual-core version of Irwindale, with 4 MB of L2 Cache (2 MB per core)
    • 2.8 GHz
    • 800 MT/s front side bus
  • Paxville MP - 90 nm process (2.67 - 3.0 GHz)
    • Introduced November 1, 2005
    • Dual-Core Xeon 7000 series
    • MP-capable version of Paxville DP
    • 2 MB of L2 Cache (1 MB per core) or 4 MB of L2 (2 MB per core)
    • 667 MT/s FSB or 800 MT/s FSB
  • Dempsey - 65 nm process (2.67 - 3.73 GHz)
    • Introduced May 23, 2006
    • Dual-Core Xeon 5000 series
    • MP version of Presler
    • 667 MT/s or 1066 MT/s FSB
    • 4 MB of L2 Cache (2 MB per core)
    • Socket J, also known as LGA 771.
  • Tulsa - 65 nm process (2.5 - 3.4 GHz)
    • Introduced August 29, 2006
    • Dual-Core Xeon 7100-series
    • Improved version of Paxville MP
    • 667 MT/s or 800 MT/s FSB

[edit] 64-bit processors: Intel64 - Intel Core microarchitecture

[edit] Xeon

  • Woodcrest - 65 nm process technology
    • Server and Workstation CPU (SMP support for dual CPU system)
    • Introduced June 26, 2006
    • Dual-Core
    • Intel Virtualization Technology, multiple OS support
    • EIST (Enhanced Intel SpeedStep Technology) in 5140, 5148LV, 5150, 5160
    • Execute Disable Bit
    • LaGrande Technology, enhanced security hardware extensions
    • SSSE3 SIMD instructions
    • iAMT2 (Intel Active Management Technology), remotely manage computers
    • Variants
      • Xeon 5160 - 3.00 GHz (4 MB L2, 1333 MHz FSB, 80 W)
      • Xeon 5150 - 2.66 GHz (4 MB L2, 1333 MHz FSB, 65 W)
      • Xeon 5140 - 2.33 GHz (4 MB L2, 1333 MHz FSB, 65 W)
      • Xeon 5130 - 2.00 GHz (4 MB L2, 1333 MHz FSB, 65 W)
      • Xeon 5120 - 1.86 GHz (4 MB L2, 1066 MHz FSB, 65 W)
      • Xeon 5110 - 1.60 GHz (4 MB L2, 1066 MHz FSB, 65 W)
      • Xeon 5148LV - 2.33 GHz (4 MB L2, 1333 MHz FSB, 40 W) -- Low Voltage Edition
  • Clovertown - 65 nm process technology
    • Server and Workstation CPU (SMP support for dual CPU system)
    • Introduced Dec 13th 2006
    • Quad Core
    • Intel Virtualization Technology, multiple OS support
    • EIST (Enhanced Intel SpeedStep Technology) in E5365, L5335
    • Execute Disable Bit
    • LaGrande Technology, enhanced security hardware extensions
    • SSSE3 SIMD instructions
    • iAMT2 (Intel Active Management Technology), remotely manage computers
    • Variants
      • Xeon X5355 - 2.66 GHz (2x4 MB L2, 1333 MHz FSB, 105 W)
      • Xeon E5345 - 2.33 GHz (2x4 MB L2, 1333 MHz FSB, 80 W)
      • Xeon E5335 - 2.00 GHz (2x4 MB L2, 1333 MHz FSB, 80 W)
      • Xeon E5320 - 1.86 GHz (2x4 MB L2, 1066 MHz FSB, 65 W)
      • Xeon E5310 - 1.60 GHz (2x4 MB L2, 1066 MHz FSB, 65 W)
      • Xeon L5320 - 1.86 GHz (2x4 MB L2, 1066 MHz FSB, 50 W)-- Low Voltage Edition

[edit] Intel Core 2

  • Conroe - 65 nm process technology
    • Desktop CPU (SMP support restricted to 2 CPUs)
    • Two CPUs on one die
    • Introduced July 27, 2006
    • SSSE3 SIMD instructions
    • Number of Transistors 291 Million
    • Intel Virtualization Technology, multiple OS support
    • LaGrande Technology, enhanced security hardware extensions
    • Execute Disable Bit
    • EIST (Enhanced Intel SpeedStep Technology)
    • iAMT2 (Intel Active Management Technology), remotely manage computers
    • LGA775
    • Variants
      • Core 2 Duo E6850 - 3.00 GHz (4 MB L2, 1333 MHz FSB)
      • Core 2 Duo E6800 - 2.93 GHz (4 MB L2, 1066 MHz FSB)
      • Core 2 Duo E6750 - 2.67 GHz (4 MB L2, 1333 MHz FSB)
      • Core 2 Duo E6700 - 2.67 GHz (4 MB L2, 1066 MHz FSB)
      • Core 2 Duo E6600 - 2.40 GHz (4 MB L2, 1066 MHz FSB)
      • Core 2 Duo E6550 - 2.33 GHz (4 MB L2, 1333 MHz FSB)
      • Core 2 Duo E6420 - 2.13 GHz (4 MB L2, 1066 MHz FSB)
      • Core 2 Duo E6400 - 2.13 GHz (2 MB L2, 1066 MHz FSB)
      • Core 2 Duo E6320 - 1.86 GHz (4 MB L2, 1066 MHz FSB)
      • Core 2 Duo E6300 - 1.86 GHz (2 MB L2, 1066 MHz FSB)
  • Conroe XE - 65 nm process technology
    • Desktop Extreme Edition CPU (SMP support restricted to 2 CPUs)
    • Introduced July 27, 2006
    • same features as Conroe
    • LGA775
    • Variants
      • Core 2 Extreme X6800 - 2.93 GHz (4 MB L2, 1066 MHz FSB)
  • Allendale - 65 nm process technology
    • Desktop CPU (SMP support restricted to 2 CPUs)
    • Two CPUs on one die
    • Introduced January 21, 2007
    • SSSE3 SIMD instructions
    • Number of Transistors 167 Million
    • LaGrande Technology, enhanced security hardware extensions
    • Execute Disable Bit
    • EIST (Enhanced Intel SpeedStep Technology)
    • iAMT2 (Intel Active Management Technology), remotely manage computers
    • LGA775
    • Variants
      • Core 2 Duo E4600 - 2.40 GHz (2 MB L2, 800 MHz FSB)
      • Core 2 Duo E4500 - 2.20 GHz (2 MB L2, 800 MHz FSB)
      • Core 2 Duo E4400 - 2.00 GHz (2 MB L2, 800 MHz FSB)
      • Core 2 Duo E4300 - 1.80 GHz (2 MB L2, 800 MHz FSB)
  • Merom - 65 nm process technology
    • Mobile CPU (SMP support restricted to 2 CPUs)
    • Introduced July 27, 2006
    • same features as Conroe
    • Socket M / Socket P
    • Variants
      • Core 2 Duo T7800 - 2.60 GHz (4 MB L2, 800 MHz FSB) (Santa Rosa platform)
      • Core 2 Duo T7700 - 2.40 GHz (4 MB L2, 800 MHz FSB)
      • Core 2 Duo T7600 - 2.33 GHz (4 MB L2, 667 MHz FSB)
      • Core 2 Duo T7500 - 2.20 GHz (4 MB L2, 800 MHz FSB)
      • Core 2 Duo T7400 - 2.16 GHz (4 MB L2, 667 MHz FSB)
      • Core 2 Duo T7300 - 2.00 GHz (4 MB L2, 800 MHz FSB)
      • Core 2 Duo T7250 - 2.00 GHz (4 MB L2, 800 MHz FSB)
      • Core 2 Duo T7200 - 2.00 GHz (4 MB L2, 667 MHz FSB)
      • Core 2 Duo T7100 - 1.80 GHz (2 MB L2, 800 MHz FSB)
      • Core 2 Duo T5600 - 1.83 GHz (2 MB L2, 667 MHz FSB)
      • Core 2 Duo T5550 - 1.83 GHz (2 MB L2, 667 MHz FSB, no VT)
      • Core 2 Duo T5500 - 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)
      • Core 2 Duo T5470 - 1.60 GHz (2 MB L2, 800 MHz FSB, no VT)
      • Core 2 Duo T5450 - 1.66 GHz (2 MB L2, 667 MHz FSB, no VT)
      • Core 2 Duo T5300 - 1.73 GHz (2 MB L2, 533 MHz FSB, no VT)
      • Core 2 Duo T5270 - 1.40 GHz (2 MB L2, 800 MHz FSB, no VT)
      • Core 2 Duo T5250 - 1.50 GHz (2 MB L2, 667 MHz FSB, no VT)
      • Core 2 Duo T5200 - 1.60 GHz (2 MB L2, 533 MHz FSB, no VT)
      • Core 2 Duo L7500 - 1.60 GHz (4 MB L2, 800 MHz FSB) (Low Voltage)
      • Core 2 Duo L7400 - 1.50 GHz (4 MB L2, 667 MHz FSB) (Low Voltage)
      • Core 2 Duo L7300 - 1.40 GHz (4 MB L2, 800 MHz FSB) (Low Voltage)
      • Core 2 Duo L7200 - 1.33 GHz (4 MB L2, 667 MHz FSB) (Low Voltage)
      • Core 2 Duo U7700 - 1.33 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)
      • Core 2 Duo U7600 - 1.20 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)
      • Core 2 Duo U7500 - 1.06 GHz (2 MB L2, 533 MHz FSB) (Ultra Low Voltage)
  • Kentsfield - 65 nm process technology
    • Two dual-core cpu dies in one package.
    • Desktop CPU Quad Core (SMP support restricted to 4 CPUs)
    • Introduced December 13, 2006
    • same features as Conroe but with 4 CPU Cores
    • Number of Transistors 586 Million
    • Socket 775
    • Variants
      • Core 2 Extreme QX6850 - 3 GHz (2x4 MB L2, 1333 MHz FSB)
      • Core 2 Extreme QX6800 - 2.93 GHz (2x4 MB L2, 1066 MHz FSB) (Apr 9th 07)
      • Core 2 Extreme QX6700 - 2.66 GHz (2x4 MB L2, 1066 MHz FSB) (Nov 14th 06)
      • Core 2 Quad Q6700 - 2.66 GHz (2x4 MB L2, 1066 MHz FSB) (Jul 22nd 07)
      • Core 2 Quad Q6600 - 2.40 GHz (2x4 MB L2, 1066 MHz FSB) (Jan 7th 07)
  • Wolfdale - 45 nm process technology
    • Die shrink of Conroe
    • Same features as Conroe with the addition of:-
      • 50% more cache, 6 MB as opposed to 4 MB
      • Intel Trusted Execution Technology
      • SSE4 SIMD instructions
    • Number of Transistors 410 Million
    • Variants
      • Core 2 Duo E8500 - 3.16 GHz (6 MB L2, 1333 MHz FSB)
      • Core 2 Duo E8400 - 3 GHz (6 MB L2, 1333 MHz FSB)
      • Core 2 Duo E8200 - 2.66 GHz (6 MB L2, 1333 MHz FSB)
      • Core 2 Duo E8190 - 2.66 GHz (6 MB L2, 1333 MHz FSB, no TXT, no VT)
  • Yorkfield - 45 nm process technology
    • Quad core CPU
    • Die shrink of Kentsfield
    • Contains 2x Wolfdale dual core dies in one package
    • Same features as Wolfdale
    • Number of Transistors 820 Million
    • Variants
      • Core 2 Extreme QX9770 - 3.2 GHz (2x6 MB L2, 1600 MHz FSB)
      • Core 2 Extreme QX9650 - 3 GHz (2x6 MB L2, 1333 MHz FSB)
      • Core 2 Quad Q9550 - 2.83 GHz (2x6 MB L2, 1333 MHz FSB)
      • Core 2 Quad Q9450 - 2.66 GHz (2x6 MB L2, 1333 MHz FSB)
      • Core 2 Quad Q9300 - 2.5 GHz (2x3 MB L2, 1333 MHz FSB)

[edit] Pentium Dual Core

  • Allendale - 65 nm process technology
    • Desktop CPU (SMP support restricted to 2 CPUs)
    • Two CPUs on one die
    • Introduced January 21, 2007
    • SSSE3 SIMD instructions
    • Number of Transistors 167 Million
    • LaGrande Technology, enhanced security hardware extensions
    • Execute Disable Bit
    • EIST (Enhanced Intel SpeedStep Technology)
    • iAMT2 (Intel Active Management Technology), remotely manage computers
    • LGA775
    • Variants
      • Intel Pentium E2200 - 2.20 GHz (1 MB L2, 800 MHz FSB)
      • Intel Pentium E2180 - 2.00 GHz (1 MB L2, 800 MHz FSB)
      • Intel Pentium E2160 - 1.80 GHz (1 MB L2, 800 MHz FSB)
      • Intel Pentium E2140 - 1.60 GHz (1 MB L2, 800 MHz FSB)

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